Comments (6)
Hi,
SpinalHDL can't realy be used in console mode in this way. You have to provide a toplevel component :
SpinalVerilog(new MyTopLevel)
And have all your hardware statements in that toplevel herarchy
Reason is that SpinalHDL has a lot of hidden stuff happening under the hood which require some setup (done by the SpinalVerilog function)
from spinalhdl.
FYI in case the sbt
startup time is annoying you and that's the reason why you want to use the REPL: you can just start sbt
once and repeatedly run runMain
, etc. in there - that makes it much quicker to use. (sorry in case you already knew)
from spinalhdl.
FYI in case the
sbt
startup time is annoying you and that's the reason why you want to use the REPL: you can just startsbt
once and repeatedly runrunMain
, etc. in there - that makes it much quicker to use. (sorry in case you already knew)
Thanks for pointing out this. Personally I prefer the console way (works like python console which I use a lot). Though '~runMain' produces immediate results, it runs the whole code and print everything all at once.
With console, it seems to be more newbie-friendly. For example, to find out the difference between 'd := a |<< c' and 'd := a << c', I can put them in console and see the difference.
from spinalhdl.
Hi,
SpinalHDL can't realy be used in console mode in this way. You have to provide a toplevel component :
SpinalVerilog(new MyTopLevel)
And have all your hardware statements in that toplevel herarchy
Reason is that SpinalHDL has a lot of hidden stuff happening under the hood which require some setup (done by the SpinalVerilog function)
Go it. Assume I'd like to learn the difference of '##' and '@@', as a newbie, the preferable way to do so is to type the following code (Pardon me if it has errors):
val a = U"8'h5"
val b = U"8'hA"
println( a @@ b )
println( a ## b)
Is there a way?
from spinalhdl.
Personnaly, i'm using Intellij Idea and that template project :
https://github.com/SpinalHDL/SpinalTemplateSbt
Else you can use sbt to generate some verilog, see the readme of that template project.
Else you can do some one liner as :
SpinalVerilog(new Component{val a = U"8'h5"; val b = U"8'hA"}).printRtl()
But the thing is that you need your repl to have the SpinalHDL compiler plugin in. i never tried.
from spinalhdl.
Personnaly, i'm using Intellij Idea and that template project : https://github.com/SpinalHDL/SpinalTemplateSbt
Else you can use sbt to generate some verilog, see the readme of that template project.
Else you can do some one liner as : SpinalVerilog(new Component{val a = U"8'h5"; val b = U"8'hA"}).printRtl()
But the thing is that you need your repl to have the SpinalHDL compiler plugin in. i never tried.
OK, i'll figure it out. Thank you Dolu.
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Related Issues (20)
- StreamFragmentWidthAdapter.make missing earlylast argument HOT 2
- How to generate RTL with parameters? HOT 2
- StreamMux with streamed select no correct join HOT 9
- WishboneSlaveFactory - doWrite is never called in pipelined mode HOT 3
- Wishbone BusIf SEL usage HOT 1
- Formal verifiation: SymbiYosys of SpinalTemplateSbt fails with "RG_WIDTH > 1 is not support by async2sync, use clk2fflogic." when using async reset
- Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys HOT 10
- Set clock domain from blackbox HOT 2
- Error when create a new ClockDomain in simulation HOT 2
- SystemVerilog Interface Support HOT 2
- NamedType returns null when called outside of a Component HOT 11
- AxiLite4SlaveFactory generates combinatorial paths from inputs to ready outputs HOT 5
- Signal naming oversights HOT 3
- `onSamplings` error when use inside clockdomain
- FiberPlugin addPrePopTask HOT 5
- Plugin deadlock in circular dependency on Handle HOT 5
- SpinalSim: onSamplings can't work properly with clock from a blackbox HOT 8
- When to override `clone`? HOT 7
- How to use Union in IO port HOT 1
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