LBUS to AXI4-Stream converter in verilog, tested in Vivado 2019.1

1. download this git repo
2. run 'make gen_ip'
3. In Vivado, using "IP Catalog" to add <path_to_this_git_repo/ip_repo> as a new user ip repository.

There are example designs for Xilinx CMAC and Interlaken IP core.

To launch simulation with CMAC, run 'make run_cmac_simulation'

To launch simulation with Interlaken, run 'make run_interlaken_simulation'

Support AXI4-Stream to LBUS and LBUS to AXI4-Stream

Support bridge with Xilinx CMAC or Interlaken core

Support both small endian and big endian for AXI4-Stream

AXI4-Stream to LBUS Latency: 0 cycle or 1 cycle (depends on if TX register is enabled)

LBUS to AXI4-Stream Latency: 0 cycle or 1 cycle (depends on if RX register is enabled)

Up to 400 MHz for xczu19eg-ffvc1760-2-i