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jonoxerohmc2022's Issues
DDS experiment for AFE net issue.
Should be run to VOUT_A and VOUT_B, not to VO_VOLUME/VO_PITCH.
Clock pin doesn't seem usable.
Unresolved question about why _G0 pin doesn't pass synthesis. Other tested options are _G1 & _G3 on revision if this isn't remediated.
Traces around USB connector.
They're OK, but look weird. Fix them.
DAC i2c Bus
Move it to i2c1 to be under control of FPGA.
Andrew is worried about the LED opening.
To test.
Gerber output of USB slots are incorrect.
It looks fine in design, but does not produce the correct output. Is this a KiCAD bug?
Junction on L802 shouldn't be there.
i2c0 net disconnect on top level sheet
Missing net labels on top sheet means i2c0 doesn't go from SAO+ connector to FPGA/AFE blocks.
Did I fix the LED pinout issue?
RA push-buttons are rubbish.
They're too small and seem fragile through both assembly and use. We need a better option.
Move i2c_1 pins to SAO header pins 5 & 6.
Andy's idea about using those pins. See pinout spreadsheet for v1.0.
Does i2c_1 need pull-ups?
Or can we implement pull-ups on FPGA. How did I not at least put place-holders..
ESD Unavailable
Need to re-design this for something which we can get and which will be less critical if not placed.
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