• useful for low frequency (e.g. 10 MHz, 100 MHz) reference with AD9910 where divide-by-four is not needed and detrimental
• also needed for bypassing the PLL at 1 GHz direct
• check loop filter/Icp usability at low frequencies

Roadmap

• add CFG bits for 1/2/4 division
• document old hardware behavior, new behavior
• expose in urukul coredevice driver
• test 1 GHz divide-by-1 PLL bypass

Not in scope:

• test 10 MHz divide-by-1 100x PLL (assuming loop filter/Icp usability)
• test 100 MHz divide-by-2 20x PLL (assuming loop filter/Icp usability)

Now that the hardware changes have landed in recent Urukul hw_revs, we can consider redesigning the CPLD gateware and the ARTIQ coredevice layer to expose more features and expose the existing ones in a better way.

Precursor changes:

• c.f. sinara-hw/Urukul#30 for the hardware changes
• #6 for IO_UPDATE decoupling that is not being used/exposed in the ARTIQ coredevice driver yet

Potential tasks

• Mirny-style SPI address-CS demux
• decouple channels
• implement independent profile/osk/attenuator
• DRG
• better RAM usage pattern

Would simplify absolute phase modes and DRG/RAM usage where IO_UPDATE is has synchronizing side-effects.
Implemented transparently and backwards compatible by blocking IO_UPDATE to channels that are not selected (if one channel is selected) and carefully placing the IO_UPDATE pulse within the CS pulse at the end of the SPI xfer.

https://github.com/quartiq/urukul/blob/master/urukul.py#L414

/cc @a-shafir

• new platform
• minimum to get the same behavior as urukul v1.3 gateware on v1.3 hardware
• Distinct from #7
• C.f. sinara-hw/Urukul#30

• reverse LED directions (Altium bug)