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urukul's Introduction

QUARTIQ Matrix Chat

Urukul CPLD code

Urukul overview

Urukul Schematics/Layout

NU-Servo

Building

Needs migen and Xilinx ISE. Assumes ISE is installed in /opt/Xilinx.

make

Flashing

With Digilent JTAG HS2 cable:

  • download firmware to dongle. Manually (adjust USB bus as needed):
/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum`

or automatically via the udev rule:

SUBSYSTEM=="usb", ACTION="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6014", ATTR{manufacturer}=="Digilent", RUN+="/usr/bin/fxload -v -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D $tempnode"
  • install xc3sprog

  • flash_xc3.sh jtaghs2

  • look for Verify: Success

License

GPLv3+

urukul's People

Contributors

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urukul's Issues

per-channel IO_UPDATE

Would simplify absolute phase modes and DRG/RAM usage where IO_UPDATE is has synchronizing side-effects.
Implemented transparently and backwards compatible by blocking IO_UPDATE to channels that are not selected (if one channel is selected) and carefully placing the IO_UPDATE pulse within the CS pulse at the end of the SPI xfer.

make the divider configurable

  • useful for low frequency (e.g. 10 MHz, 100 MHz) reference with AD9910 where divide-by-four is not needed and detrimental
  • also needed for bypassing the PLL at 1 GHz direct
  • check loop filter/Icp usability at low frequencies

Roadmap

  • add CFG bits for 1/2/4 division
  • document old hardware behavior, new behavior
  • expose in urukul coredevice driver
  • test 1 GHz divide-by-1 PLL bypass

Not in scope:

  • test 10 MHz divide-by-1 100x PLL (assuming loop filter/Icp usability)
  • test 100 MHz divide-by-2 20x PLL (assuming loop filter/Icp usability)

SPI readback tests don't pass

~/Build/Source/urukul ((v1.3.1) $%)$ python urukul_sim.py
Traceback (most recent call last):
  File "urukul_sim.py", line 130, in <module>
    main()
  File "urukul_sim.py", line 126, in main
    special_overrides={Tristate: SimTristate, Instance: SimInstance})
  File "/Users/dpn/Build/Source/migen/migen/sim/core.py", line 414, in run_simulation
    s.run()
  File "/Users/dpn/Build/Source/migen/migen/sim/core.py", line 403, in run
    self._process_generators(cd)
  File "/Users/dpn/Build/Source/migen/migen/sim/core.py", line 357, in _process_generators
    request = generator.send(reply)
  File "urukul_sim.py", line 105, in test
    assert ret & 0xff0000 == 0x080000, hex(ret)
AssertionError: 0x2468ac

Redesign

Now that the hardware changes have landed in recent Urukul hw_revs, we can consider redesigning the CPLD gateware and the ARTIQ coredevice layer to expose more features and expose the existing ones in a better way.

Precursor changes:

  • c.f. sinara-hw/Urukul#30 for the hardware changes
  • #6 for IO_UPDATE decoupling that is not being used/exposed in the ARTIQ coredevice driver yet

Potential tasks

  • Mirny-style SPI address-CS demux
  • decouple channels
  • implement independent profile/osk/attenuator
  • DRG
  • better RAM usage pattern

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