Comments (3)
I think the begin
is not legal SystemVerilog. It is generate
/endgenerate
(https://www.systemverilog.io/generate). Or http://courses.eees.dei.unibo.it/LABMPHSENG/wp-content/uploads/2016/02/SystemVerilog_3.1a.pdf A.4.2.1 Generated module instantiation.
from morty.
This error is from the parser, indicating an error in your code. It seems the begin : t
and corresponding end
of your code are not spec-compliant. Removing these should fix your issue, although I see the repository you have linked is deprecated.
Morty uses sv-parser to parse the files, which analyzes all files according to the systemverilog specification. Unfortunately we will not modify morty to work around the parser or work to patch the parser for not spec-compliant code.
from morty.
Hi Florian, thank you for your answer!
Given that this pattern is present in the wild and accepted by other tools (I tried Verilator for example), do you think it should be accepted by Morty as well?
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Related Issues (20)
- Fix missing re-naming of optional endlable
- Also rename interfaces
- Re-enable minimization and keeping comments HOT 1
- Improve error handling
- [RFC]: Parse documentation HOT 1
- Only re-name defined modules HOT 1
- Comments after string literals
- Add anchor symbols to paragraph headings
- We are currently using `signal` as prefix in the ID of all `VarItems`. I wonder if we should change that to `var` to be closer to the language.
- Not directly related, but all those `<h3 ...` strings are very similar and their construction should be refactored IMO.
- Parsing fails for defines as keys in case statement HOT 3
- Issue with parsing some generate statements HOT 2
- defines and compile order HOT 1
- Multiple declarations of the same module builds a bad module graph
- $fatal guarded by synopsys translate_off/on` causes parse error HOT 3
- Morty panic HOT 2
- ifndef vanishes from includes HOT 3
- Morty stack overflow HOT 14
- Parse error of SystemVerilog set membership operator 'inside'
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