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a2o

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

basejump_stl_cores

BaseJumpSTL cores for FuseSoC

black-parrot

A Linux-capable RISC-V multicore for and by the world

black-parrot-subsystems

blindtest-spotify

Simple blindtest app connected to Spotify

cellift-yosys

CellIFT implementation inside Yosys

common_cells

Common SystemVerilog components

common_verification

SystemVerilog modules and classes commonly used for verification

contactssaver

cores-veer-el2

VeeR EL2 Core

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cva6_yosys_issue

A repository to reproduce the Yosys issue with CVA6

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

cxxrtl-b1

cxxrtl-b2

cxxrtl-b3

cxxrtl-b4

cxxrtl-b5

cxxrtl-b6

difuzz-rtl

flavibird

flaviens.github.io

fourbix

Plateforme de prêts et gestion des matériels des binets. Projet Modal Web INF473W.

fpu_div_sqrt_mvp

[UNRELEASED] FP div/sqrt unit for transprecision

gravitree

hackathon_rules

hardfloat

hardfloat-cores