pruthvi1990 / dataflowgraph-modeling-for-logic-circuits Goto Github PK

This project is about designing and generating synthesizable high level state machine description from the Data flow graph in Verilog while providing scheduling alternatives like LIST_L and LIST_R using modeling Paradigm. The user can construct Data flow graph (for ex data flow graph for 6th order FIR filter) using Atoms. Atoms can be logical operators such as adder, subtractor and multipliers etc. Atoms act as graph nodes and the edges can be used to define the relationship between them in the Data flow graph.