Tested via the current official MisterFPGA update, the speedometer needle is showing as artifacty blocks only. The rest of the game seems to work fine.
There's no indication of active low or high in the 68k module port definition. I recently tried to use this in a project and assumed it was low. No activity when the CPU was hooked up.
Double checked when using the 68k module in quartus, there's no errors when building (thought it might not be finding the micro code files). Possible to comment the in/out in the 68k module so the manual can be referenced? Thank you for your work @nukeykt.
I'm trying to port your code to MiSTer. But for a better adoption it would be good to have additional signals:
HBlank, VBlank. Also pixel enable reflecting a current pixel clock since MD may have not only a different pixel clock but even it changes during the line.
Also it would be good to have some CART data request signal as earlier as possible since i need to retrieve the data from SDRAM which requires some time. This signal should be either address strobe or toggling with every request, so it can be distinguished from 2 sequential requests.