The project aims to design a Pipelined 32-Bit MIPS Micro-Processor (RISC-Like Harvard Architecture), Using Verilog HDL. It has early branch prediction and provides a hazard control unit that handles both data and control hazards by (Forwarding, Stalling, Flushing), the processor is simulated on ModelSim tool. To test the design the processor is simulated on ModelSim tool.
I ran the following programs:
-Get the factorial of 8.
-Get greatest common divisor between 120 and 180.
-Get the Fibonacci sequence.