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100daysofrtl

100 Days of RTL

al-folio

A beautiful, simple, clean, and responsive Jekyll theme for academics

arm

ARM processor model

beg_mod_cpp

Source code for demos in Complete Modern C++ course.

cocotb-example

computerarchitecture

Works of all the labs of Computer Architecture. Contains single-cycle, and pipelined ARM architecture verilog code.

fpga_workshop_collaterals

Input files and commands needed for the workshop, sorted daywise

hw_interview_questions

A collection of commonly asked RTL design interview questions

jekyll-theme-chirpy

A minimal, sidebar, responsive web design Jekyll theme, focusing on text presentation.

litex

Build your hardware, easily!

mystic_riscv64

64-bit RISC-V processor

oh

Verilog library for ASIC and FPGA designers

opencl-cnn-accelerator

OpenCL based CNN Accelerator on Intel DE10 Nano FPGA.

pcievhost

PCIe (1.0a to 2.0) Virtual host model for verilog

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

piplined_mips_microprocessor

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

risc-v_myth_workshop

Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for Me in Thirty Hours" Workshop

riscv_workshop_collaterals

This repository is created for conducting RISC-V 5-day workshops

simplecpu

An open source CPU design and verification platform for academia

tbengy

Python Tool for UVM Testbench Generation

vproc

Virtual processor co-simulation element for Verilog and VHDL environments