mabrains / sky130_klayout_pdk Goto Github PK

How can we add pins so we can recognize the ports of the device?

KLayout version 0.27.8 (fresh install)
Sky130 PDK 9d36065
Python 3.8.10
Linux 5.13.0-30-generic #33~20.04.1-Ubuntu SMP Mon Feb 7 14:25:10 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux

Trying to place a nmos, I get the following error (and nothing happens):

ERROR: invalid literal for int() with base 10: 'Connection Up' in PCellDeclaration.produce
  /home/llandsmeer/.klayout/tech/sky130/pymacros/sky130_pcells/nmos18.py:123
  :/built-in-pymacros/pcell_declaration_helper.lym:185

Platform

Ubuntu 22.04
Klayout 0.28.5
sky_130_klayout_pdk latest from git

Steps to Reproduce the Problem

Run

KLAYOUT_HOME=./sky130_tech/ klayout -e

The following error messages are shown in terminal

ERROR: Reading /home/vvk/sky130_klayout_pdk/sky130_tech/tech/sky130/lvs/sky130.lylvs: XML parser error: error occurred while parsing element in line 31, column 49
ERROR: Reading /home/vvk/sky130_klayout_pdk/sky130_tech/tech/sky130/lvs/sky130.lylvs: XML parser error: error occurred while parsing element in line 31, column 49
ERROR: /home/vvk/sky130_klayout_pdk/sky130_tech/tech/sky130/pymacros/sky130.lym:9: No module named 'cells'
  /home/vvk/sky130_klayout_pdk/sky130_tech/tech/sky130/pymacros/sky130.lym:9 (class ModuleNotFoundError)

The first two are related to #28. But what is the No module cells error?

Our Magical team is currently working on supporting skywater-pdk to enable open-sourced tape out design. We have already finished the PMOS and NMOS device generation part, and are in desperate need of your support for the resistor and capacity LVS file to further boost the impact of both your open-sourced skywater-pdk and our Magical tool. Could you provide the resistor and capacitor LVS file? We also need parasitic extraction to generate the analog IC layout automatically.

Thanks for your help.

Root cause

Angle brackets in copyright comment result in XML parser error:

> ...
> # You should have received a copy of the GNU Affero General Public License
> # along with this program.  If not, see <https://www.gnu.org/licenses/>.

Actual Behavior

ERROR: Reading .../klayout_sky130/sky130_tech/tech/sky130/lvs/sky130.lylvs: XML parser error: error occurred while parsing element in line 31, column 49

Steps to Reproduce the Problem

1. Run:
   > KLAYOUT_HOME=./sky130_tech klayout -e

Specifications

• Version: Latest
• Platform: Ubuntu 22.04.1 LTS

@mohanad0mohamed Hello, Is it possible to let me know where did you find the gds files that you have here? I can't find these in the Skywater repository.

Hi ,

Trying to use a VIA - metal1 metal2 VIA. But Seems following DRC exists.

m2.5 [via_new]
m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um
polygon: (0.425,-0.395;0.425,-0.245;0.575,-0.245;0.575,-0.395)

Thanks

Hi. Your repo mentions that for most of the devices are verified by "semi-automatic". Does that include automated LVS scripts that extract resistor/capacitor devices? It seems that I am unable to find how res/cap are extracted in your LVS script: https://github.com/mabrains/sky130_klayout_pdk/blob/main/lvs/lvs_sky130.lylvs

Thanks for the help.

• Simplify Pcells. How could we simplify the Pcells code by adding different levels of hierarchy? For example, Pcells could be greatly simplified
• how can we make them available through PyPi and Klayout package manager? We could add them as PRs to this repo, which has both
• Write tests and documentation
• add ports so we can route and connect different PCells