mabrains Goto Github PK

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Main Github Repo

a25_coprocessor

Implementation of amber25 of ARM processor using OpenLANE and skywater PDK, the coprocessor block

ahkab

a SPICE-like electronic circuit simulator written in Python

align-public

ampse

This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download IPs generated by AMPSE or parameterized IPs with neural network based parameter-metric regression models. Watch this repository and follow USCPOSH on GitHub for our further updates! USC POSH Group: https://githu

ams_kgd

A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.

amsat_txrx_ic

An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)

analog-rf-testchip

Analog and RF blocks for Skywaters 130nm Technology Designed by Mabrains Teams

analog_blocks

Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.

analog_design_internship

Analog Design Internship using Skywater 130nm

arty-mpw-tester

avsdpll_1v8

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

awesome-semiconductor-startups

List of awesome semiconductor startups

awesome_ai4eda

biogpt

black-parrot

A Linux-capable RISC-V multicore for and by the world

build_mabrains_packages

All Mabrains Docker Images Build Process

cad_engineers_training_materials

caplet

GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.

caravel-lite

caravel_analog_rf

Analog and RF blocks on Skywaters 130nm

caravel_user_project_analog_ldo_dpll

Skywater 130nm LDO parts and DPLL

caravel_user_project_ldo

Completed LDO Design for Skywaters 130nm

caravel_user_project_ldo_dpll

caravel_user_project_mabrains

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel3

Chisel 3: A Modern Hardware Design Language

coderl

This is the official code for the paper CodeRL: Mastering Code Generation through Pretrained Models and Deep Reinforcement Learning (NeurIPS22).

colossalai

Making big AI models cheaper, easier, and more scalable

conda-eda

Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.