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The ADS8686 channel 'A', 'B' are stored into the DDR at different 'cycle_cnts'. This was causing slight errors in impedance analyzer measurements until I shifted the channel 'A' results one cycle.

Instead in the FPGA code, we should store 'A', 'B' results at the same cycle count so that there is no need to synchronize in software. (Unfortunately, this will require edits to the function to read .h5 files data_to_names and will make old .h5 files incompatible with newer .h5 files).

A synchronous always block sensitivity list can have a clock or a clock and a reset. A third signal in the sensitivity list is not good practice.

    //state register
    always@(posedge rst or posedge clk or posedge startread/*int_o*/)begin

This issue is to remove posedge startread from the sensitivity list

Either, move startread out of the sensitivity list and into the logic of the state register always block
Or, move startread into the next state logic.

A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <A1_DCO_P> is placed at site

The OpalKelly device has 8 LEDs. Use these to indicate status.

Need to use the OpalKelly register API for setting various configuration bits.

OK registers with BRAM

To allow Python to import the ok module on MAC change the interfaces.py file to:

# TODO: make sure this path works for Windows, Mac, and Linux: https://docs.opalkelly.com/fpsdk/frontpanel-api/programming-languages/
if sys.platform == 'win32':
    sys.path.append(os.path.join(configs['frontpanel_path'], 'API/Python/3.7/x64')) # Add path to ok.py to PATH for import
    os.add_dll_directory(os.path.join(configs['frontpanel_path'], 'API/lib/x64'))   # Make DLL (okFrontPanel.dll) available
elif sys.platform == 'darwin':
    sys.path.append(os.path.join(configs['frontpanel_path'], 'API/Python3/')) # Add _ok.so to PATH for import

At line 43 of DAC80508_ADS8686_test.py an instrument is opened:

dc_pwr, dc_pwr2 = open_rigol_supply(setup=pwr_setup) # 7V and +/-16.5V, None

This fails during pytest collection on a Mac when not connected to the instrument. python3 -m pytest -m no_fpga

I explored the pytest flag of --continue-on-collection-errors yet this did not remove the error since a Fatal Python error occurs.

Would it be possible to move open_rigol_supply to a fixture/function so that it only happens if the test is run (rather than just collected?)

The terminal error message:

A00080338:python koer2434$ python3 -m pytest --continue-on-collection-errors -m no_fpga
============================================================= test session starts ==============================================================
platform darwin -- Python 3.9.7, pytest-7.1.2, pluggy-1.0.0
rootdir: /Users/koer2434/Documents/covg_fpga, configfile: pyproject.toml
plugins: anyio-3.5.0
collecting ... Fatal Python error: Aborted
Current thread 0x000000011602a600 (most recent call first):
File "/Users/koer2434/opt/anaconda3/lib/python3.9/site-packages/pyvisa/ctwrapper/functions.py", line 1871 in open_default_resource_manager
File "/Users/koer2434/opt/anaconda3/lib/python3.9/site-packages/pyvisa/highlevel.py", line 3024 in new
File "/Users/koer2434/opt/anaconda3/lib/python3.9/site-packages/instrbuilder/scpi.py", line 674 in open_visa
File "/Users/koer2434/opt/anaconda3/lib/python3.9/site-packages/instrbuilder/scpi.py", line 651 in init
File "/Users/koer2434/opt/anaconda3/lib/python3.9/site-packages/instrbuilder/scpi.py", line 975 in init_instrument
File "/Users/koer2434/opt/anaconda3/lib/python3.9/site-packages/instrbuilder/instrument_opening.py", line 273 in open_by_name
File "/Users/koer2434/Documents/covg_fpga/python/instruments/power_supply.py", line 10 in open_rigol_supply
File "/Users/koer2434/Documents/covg_fpga/python/tests/integration_tests/DAC80508_ADS8686_test.py", line 43 in
File "/Users/koer2434/opt/anaconda3/lib/python3.9/site-packages/_pytest/assertion/rewrite.py", line 168 in exec_module
File "", line 680 in _load_unlocked
File "", line 986 in _find_and_load_unlocked
File "", line 1007 in _find_and_load
File "", line 1030 in _gcd_import
File "/Users/koer2434/opt/anaconda3/lib/python3.9/importlib/init.py", line 127 in import_module
File "/Users/koer2434/opt/anaconda3/lib/python3.9/site-packages/_pytest/pathlib.py", line 533 in import_path

Lines 33 and 34 state:

reg startread = 1'b0;
reg readmarker = 1'b0;

This may work in simulation but is not necessarily synthesizable. In hardware (i.e. on the FPGA), if you desire a register to be initialized to a certain value a flip-flop with a reset is needed. However, in certain scenarios, a reset may not be needed if all the inputs that create this signal initialize to known values.

Action items for this issue:

1. See if this synthesizes onto the FPGA
2. Think through if it is necessary to initialize these regs
3. If it is not, necessary remove the initialize
4. If it is, consider how to add into a flip-flop with a reset

Could not import ok when using Windows and anaconda 3.9.7
Similar issues seem to have been noticed by the scipy community:

• ddl_add_directory issues

In addition add the DDL directory to the path using:

    os.environ.setdefault('PATH', '')
    os.environ['PATH'] += os.pathsep + dll_dir

As explained at the bottom of this issue

There can be confusion when we don't know what version of Verilog code a bit file originated from.
I'd propose that we use the MD5 checksum, after skipping the header information that contains the date/time of the build, to create a unique ID for bit files.
See this Xilinx Answer

$ tail -c 4045674 fpga1.bit | md5sum

We should remove:

• _ok.so
• ok.py
• okFrontPanel.dll

We should also remove

• _ok.pyd and add extensions *.pyd to gitignore

daq.set_dac_gain(channel, 5) # 5V to see easier on oscilloscope
has an incorrect channel mapping. Channel 0 actually changes channel 1, and channel 1 changes channel 0. Need to correct the I/O expander nibble to channel mapping within the boards.py file.
Suspect this caused similar issues with the ISEL programming for the Howland current pump.

These two code blocks seem to be generating a pulse that is one clock cycle wide (startread) on the rising edge of int_o:

  always@(posedge clk /*or posedge int_o*/) begin
      if(int_o && !readmarker)begin
         startread <= 1'b1;
         readmarker <= 1'b1;
      end
      else if(!int_o)begin
          readmarker <= 1'b0;
      end
      /*else begin
         startread <= 1'b0; 
      end*/
  end

always@(negedge clk)begin
	if(startread)begin
		startread <= 1'b0;
	end
	else begin
		startread <= startread;
	end
end

A best practice "rule" relevant here is to not mix positive edge and negative edge clock triggers, particularly for flip-flops driving the same signal.

A better approach follows the answer from Dave Tweed in this StackExchange answer

So this issue is to change the creation of startread to use a 2-stage synchronizer.

The _ok.so shared library needs to be able to find libokFrontPanel.dylib

The user should navigate to the FrontPanel API directory: e.g. frontpanel_5p26/API/Python3/ and check where _ok.so is searching for libokFrontPanel.dylib

In a terminal:

A00080338:Python3 koer2434$ otool -L _ok.so
_ok.so:
libokFrontPanel.dylib (compatibility version 0.0.0, current version 0.0.0)

This output indicates that the Python import of ok will fail since libok is one directory up.

Change using install_name_tool
In terminal:
install_name_tool -change libokFrontPanel.dylib /fullpath/to/libokFrontPanel/libokFrontPanel.dylib _ok.so

Alternatively, the path to libokFrontPanel.dylib could be included in the environmental variable DYLD_FALLBACK_LIBRARY_PATH as discussed at Is it OK to use DYLD_LIBRARY_PATH on Mac OS X? And, what's the dynamic library search algorithm with it?

The ADS8686 sequencer free runs at 1 MSPS. We need to implement a small module count of conversion starts in the FPGA that allows us to map each DDR reading to a specific ADS MUX channel within the sequencer sequence.
The counter should only be reset when the ADS8686 is also reset.

DDR data streams are very long and normally have a repeated value for many many points. We should create a method to find the unique points in a DDR sequence and plot lines between these rather than all points.