Comments (1)
This is addressed and tested (fixed impedance analyzer issues) in the ads_sync branch.
from covg_fpga.
Related Issues (19)
- Implement Opal Kelly registers
- Fast DAC signal playback
- Module for setting and reading generic I/O levels
- Still alive and state using LEDs
- WbSignal_converter: create 1 clock cycle pulse
- Wb_SignalConverter: avoid reg initializations HOT 1
- Wb_SignalConverter: state register sensitivity list
- LVDS needs to be on clock pin?
- Opal Kelly files should be removed from the repository HOT 1
- DAC80508_ADS8686_test.py executes open_rigol_supply fails during pytest collection HOT 3
- MAC installation instructions HOT 1
- Add MAC frontpanel setup to interfaces.py HOT 1
- os.add_dll_directory does not work as expected on Windows with anaconda HOT 1
- DAQ board set_dac_gain
- ADS8686 sequencer position is unknown in DDR readings HOT 1
- Determine FPGA bit-file version
- Standardize Xilinx synthesis and elaboration options
- Plotting of DDR data streams is too memory intensive HOT 3
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from covg_fpga.