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rvv-intrinsic-doc

rvvi

RISC-V Verification Interface

s1_core

S1 Core

sail-riscv

Sail RISC-V model

sak-deprecated

SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA

salsa20

Salsa20StreamCipher

sammy

Sammy is a tiny javascript framework built on top of jQuery, It's RESTful Evented Javascript.

sancus-compiler

Secure compilation of annotated C code to protected modules

sancus-core

Minimal OpenMSP430 hardware extensions for isolation and attestation

sancus-examples

Examples and test suite

sancus-main

Top-level repository and build script

sancus-support

Untrusted support software and device drivers

sap

8-bit uP

sap-1-v2-mojo

SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.

sap.gui.scripting.net

sardmips

SardMIPS

sarm7tm

No description

sasc

Simple Asynchronous Serial Controller

sata_controller_core

Serial ATA Host Bus Adapter Core for Virtex 6

sata_phy

SATA PHY

sbc6502

Single Board Computer based on 6502 CPU

sbd_sqrt_fp

No description

sbemimage

Versatile acquisition software for serial block-face electron microscopy

sc2v

SystemC to Verilog Synthesizable Subset Translator

scala-x86-gen

Generates x86 instruction code

scala-x86-inst

Contains all the code for x86 instructions!

scamp-cpu

A homebrew 16-bit CPU with a homebrew Unix-like-ish operating system.

scan_based_serial_communication

Scan Based Serial Communication

scarm

scARM - A SystemC ARM

scarts

Scarts Processor