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Loester Franco's Projects

riscv-v-spec icon riscv-v-spec

Working draft of the proposed RISC-V V vector extension

riscv_vhdl icon riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

riscvspecformal icon riscvspecformal

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

riscy icon riscy

Riscy Processors - Open-Sourced RISC-V Processors

rocket.chat icon rocket.chat

The ultimate Free Open Source Solution for team communications.

rosetta icon rosetta

ROSETTA Configurable Dot Matrix Display Controller

rotinom icon rotinom

AGC Test Connector Electrical Simulation Board

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