Comments (1)
Tried to address this with the key_exp_piplining branch. I suggest we close this as a will-not-fix.
Summary of the results
- Key expansion pipelining is feasible and we have a working implementation
- Integration into the encoder is possible, as each key is generated on the fly for each round (or sometimes in advance of a round). This resulted in a buffer of keysize between each round, instead of NUM_ROUNDS * keysize.
- Integration into the decoder is not possible, and is discouraged in the literature. The issue is that you need the keys in reverse order, i.e. for decoder round 0 you need the last round key. Since each round key is dependent on the previous round keys, you must calculate them all during the first round, like we had before.
We tried a hybrid approach, where the pipelined module was used in the encoder and the single cycle module was used in the decoder. This asymmetry introduced additional problems such as an additional pipeline stage some complexity in the assertions.
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Related Issues (20)
- Investigate "0-in" setup for emulation assertion usage HOT 1
- Investigate additional SCEMI Pipes options HOT 1
- Create Need For Speed Proposal HOT 7
- Implement code coverage HOT 4
- Modify Transactor to test all 3 AES version in parallel HOT 2
- Improve usage of valid bit propogation through modules HOT 3
- Enable Questa Simultion Profiling HOT 1
- Add capability to top level testbench for "seeded tests" HOT 4
- Update HVL testbench to do directed and then seeded testing HOT 3
- Create decoder->encoder in Transactor to utilize other data in the test vector HOT 1
- Change generated vector format HOT 4
- ExpandKey test bench produces a stack trace HOT 3
- Modify make file to only run top level testbench once HOT 1
- Update block diagrams HOT 3
- Compile time selection to infer RAM or not for LUTs HOT 1
- Modify seeded testing to use encrypted data HOT 1
- Investigate other ways to transfer data to the emulator HOT 2
- Add additional assertions HOT 1
- Add additional background information to the final paper HOT 2
- Add assertion negative testing HOT 2
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