Comments (4)
Low priority.
from aes-processor.
@kinap Initial attempt to implement and test code coverage at the buffered round module level resulted in a huge number of "coverage bins" because of the module replication at the higher level and also the multiple instantiations. This resulted in a very long compile time (52 mins) as well as an increase in the Veloce emulator runtime. I'll reconsider my strategy and try implementing the code coverage at a higher level and see if I can get something meaningful working tomorrow.
from aes-processor.
I tried implementing code coverage at the higher level. I wasn't able to anything fancier than making sure that each byte of the key and each byte of the data in were covered by each permutation of the byte. I experimented with using cross statements on a subset of the data but that made the design require 4 logic boards.
It adds a lot to the compile time and I don't think it really adds that much value to our project. @kinap If you are okay with it I'll just close this out and not add any of the coverage stuff.
from aes-processor.
Closing this out as a nice idea that is difficult to efficiently implement on the emulator.
from aes-processor.
Related Issues (20)
- Investigate "0-in" setup for emulation assertion usage HOT 1
- Investigate additional SCEMI Pipes options HOT 1
- Create Need For Speed Proposal HOT 7
- Modify Transactor to test all 3 AES version in parallel HOT 2
- Improve usage of valid bit propogation through modules HOT 3
- Enable Questa Simultion Profiling HOT 1
- Add capability to top level testbench for "seeded tests" HOT 4
- Update HVL testbench to do directed and then seeded testing HOT 3
- Create decoder->encoder in Transactor to utilize other data in the test vector HOT 1
- Change generated vector format HOT 4
- ExpandKey test bench produces a stack trace HOT 3
- Modify make file to only run top level testbench once HOT 1
- Update block diagrams HOT 3
- Compile time selection to infer RAM or not for LUTs HOT 1
- Modify seeded testing to use encrypted data HOT 1
- Investigate other ways to transfer data to the emulator HOT 2
- Add additional assertions HOT 1
- Add additional background information to the final paper HOT 2
- Add assertion negative testing HOT 2
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