Add capability to top level testbench for "seeded tests" about aes-processor HOT 4 CLOSED

@SLawson @kinap I got something working for this last night that I need to polish up but I was able to get a 46% utilization rate on the emulator (up from under 1%) and I think this could be improved since I'm generating 128 test cases from the base and could do more.

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@pear7 Wow, that's a great increase.

How are you permuting the data to create new test cases?

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I've got a bounded for loop in the Transactor that takes the base test case
and flips each bit one at a time in the input data while keeping the key
constant and pushes one of these new test cases each clock cycle.

I've almost got the assertion working to verify end to end
plain->encrypted->plain but need to add a buffer for the key value to make
sure the timing is correct. I've also added "muxes" to change where the
signals are being driven from which allows us to change "modes" where some
test cases verify the encrypted data and some test cases just verify the
end to end plain text encryption/decryption and have the assertions setup
to switch modes.

On Sun, Aug 21, 2016 at 1:13 PM, Daniel Collins [email protected]
wrote:

@pear7 https://github.com/pear7 Wow, that's a great increase.

How are you permuting the data to create new test cases?

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Resolved w/ 05cfb62. Currently to access, change the line in the HVL testbench from test.testType = DIRECTED to test.testType = SEEDED. HVL testbench will be updated as part of #24.

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