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jbush001 avatar jbush001 commented on May 26, 2024

Prototype implementation here:
https://gist.github.com/jbush001/636812836911d5c7873893a1d0ae517e

from nyuziprocessor.

jbush001 avatar jbush001 commented on May 26, 2024

A few alternatives (which are not mutually exclusive):

  • Have a chunk of shared SRAM, accessible both by coprocessors and the nyuzi cores.
  • Create a general purpose coprocessor instruction that has an operation field.

from nyuziprocessor.

jbush001 avatar jbush001 commented on May 26, 2024

On SRAM: this solution would look similar to the proposal in implementation, and could be implemented using the proposal. However, the proposal is more general.
On instruction: one big issue is that an access control model would need to be defined. The instruction could be made supervisor-only, but that might incur an unreasonable performance penalty for some configurations. The advantage of memory mapping is that the existing MMU access control model can be reused.

from nyuziprocessor.

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