Comments (3)
Prototype implementation here:
https://gist.github.com/jbush001/636812836911d5c7873893a1d0ae517e
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A few alternatives (which are not mutually exclusive):
- Have a chunk of shared SRAM, accessible both by coprocessors and the nyuzi cores.
- Create a general purpose coprocessor instruction that has an operation field.
from nyuziprocessor.
On SRAM: this solution would look similar to the proposal in implementation, and could be implemented using the proposal. However, the proposal is more general.
On instruction: one big issue is that an access control model would need to be defined. The instruction could be made supervisor-only, but that might incur an unreasonable performance penalty for some configurations. The advantage of memory mapping is that the existing MMU access control model can be reused.
from nyuziprocessor.
Related Issues (20)
- Switch to github actions for CI build.
- Is this project going to support the openCL? HOT 2
- I saw a similar crash in the user_copy_fault test. HOT 2
- I want to use quartus to generate the RTL of GPU HOT 3
- Error building NyuziProcessor (probably NyuziToolchain) HOT 16
- Crash w/ latest version of Verilator
- Is there a problem with these lines of code in cache_lru.sv or is it just that I don't understand the algorithm? HOT 2
- Suggestions HOT 1
- hi how can i get linux driver HOT 3
- May be a icache miss thread still can be scheduled again? HOT 3
- Khronos ML summit HOT 2
- run_fpga command does not work properly for me HOT 6
- 00000000 Did not get ack for load memory, got c8 instead HOT 7
- make error HOT 6
- setup_tools.sh failure HOT 10
- ./scripts/setup_tools.sh error on MAC M1 HOT 2
- Questions related to integration. HOT 1
- TARGET_FILE:llvm-strip : build error HOT 1
- Performance measure using hash program HOT 8
- solution of ASM compiler identification is unknown
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