make error about nyuziprocessor HOT 6 CLOSED

It appears you are using the Xilinx tools here and have created your own build files (rather than the Altera/Quartus configuration that is in the repo). The Xilinx tools handle some cases in the language differently and apparently are more picky than the Quartus tools in this one. Specifically, the problem here seems to be that the Quartus tools will implicitly zero pad an assignment if the sizes aren't the same, whereas the Xilinx tools won't. In this case, the comparison result is 16 bits, but the writeback bus is 512 bits wide.

I don't have the Xilinx tools installed to test this, but I can suggest that you could pad the values out explicitly, something like:

                writeback_value_nxt = vector_t'({496'd0, mcycle_vcompare_result});

or perhaps assign only the low bits, i.e.:

                writeback_value_nxt[0] = {16'd0, mcycle_vcompare_result };

from nyuziprocessor.

It appears you are using the Xilinx tools here and have created your own build files (rather than the Altera/Quartus configuration that is in the repo). The Xilinx tools handle some cases in the language differently and apparently are more picky than the Quartus tools in this one. Specifically, the problem here seems to be that the Quartus tools will implicitly zero pad an assignment if the sizes aren't the same, whereas the Xilinx tools won't. In this case, the comparison result is 16 bits, but the writeback bus is 512 bits wide.

I don't have the Xilinx tools installed to test this, but I can suggest that you could pad the values out explicitly, something like:

                writeback_value_nxt = vector_t'({496'd0, mcycle_vcompare_result});

or perhaps assign only the low bits, i.e.:

                writeback_value_nxt[0] = {16'd0, mcycle_vcompare_result };

This is the process when I build this project. My settings are default. And I just try your method but no useful for this error like this below.

from nyuziprocessor.

Okay, I was thrown because this was in a directory called 'FPGA_ZYNQ_IC_Learn'. It looks like maybe this is failing in Verilator? Can you type the following on the command line?

verilator --version

from nyuziprocessor.

sry I just forgot telling you my environment, I work in the Ubuntu18.04 in WSL. The 'FPGA_ZYNQ_IC_Learn' directory is just a name which mounting on the disk. And the verilator version like below:
root@DESKTOP-355QV49:/mnt/g/FPGA_ZYNQ_IC_Learn/IC/learn_project/GPU/NyuziProcessor# verilator --version
Verilator 4.210 2021-07-07 rev v4.210

from nyuziprocessor.

Thanks, that's helpful. The issue appears to be that you have a newer version of Verilator installed on your system than this was originally built with, and the latest version is stricter about how it handles casting. I have modified the Verilog to do this more cleanly, and run unit tests against the old Verilator to ensure it didn't introduce regressions, but haven't been able to test against the new version of Verilator, so no guarantees. Please sync to the latest revision and try again.

(the setup.sh does attempt to install a compatible version of Verilator, but, if there is another version installed, that can take precedence. Another potential remedy, if my patch above doesn't work. would be to uninstall the other system version and rerun setup.sh to install the older version).

I hope that helps.

from nyuziprocessor.

Closing for now, as this should address the issue, but feel free to reopen if it is still a problem.

from nyuziprocessor.