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jbush001 avatar jbush001 commented on June 25, 2024

When running in the testbench, the VGA signals aren't going to show anything interesting. That module is usually disabled, and, when it is not, the simulation doesn't run long enough to display interesting data, as will spend many cycles in the vblank (that module exists just to debug the memory transactions).

As for the other issues: these are very strange. To start out, have you made any changes to the code (could you do a quick 'git diff' to check)? Which version of the Quartus tools are you using?

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ergintr avatar ergintr commented on June 25, 2024

Thanks for reply,
I use QUARTUS Lite 20.1 version. I have made the following changes :

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jbush001 avatar jbush001 commented on June 25, 2024

Ah, thanks.

  1. The graphics seem to only be yellow and white, which suggests the R and G lines aren't connected properly (stuck at 1), with only the B line connected. I'd suggest checking the pin configuration.
  2. I don't believe the current SDRAM controller will work correctly if configured for 16 bits, as it doesn't handle the bus width and SDRAM width being different. This was a quick and dirty controller to bring up on my board, so it was hard coded as such. I'm a bit surprised this configuration works at all. If you can find another SDRAM module with an AXI interface (for example, I think Quartus may have one in their library), that might be easier, otherwise this would need a bit more logic to latch the upper and lower half words before putting them into the load_fifo (and likewise for stores).

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jbush001 avatar jbush001 commented on June 25, 2024

Closing, as this is an unsupported configuration.

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ergintr avatar ergintr commented on June 25, 2024

Thank you, for your help Sir.

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jbush001 avatar jbush001 commented on June 25, 2024

Sorry there wasn't a better answer.

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