jbrzusto / digdar Goto Github PK
View Code? Open in Web Editor NEWfork of red pitaya dedicated to digitizing pulsed marine radar
License: GNU General Public License v2.0
fork of red pitaya dedicated to digitizing pulsed marine radar
License: GNU General Public License v2.0
jbrzusto/ogdar will use zero as a sentinel value indicating "not a sample" to recognize metadata or uninitialized regions in the sample buffer.
These are signed but apparently being plotted as unsigned, or something like that, because
the display saturates at both ends.
t=0
are later in time, not earlier, because trigger detection is what starts filling the buffer in our FPGA build.ARP is not always detected, and not always at same location, so:
SWEEP_COUNTER uint32
records number of times ACP count has wrapped past a specified value (e.g. 450 for Furuno, 4096 for Bridgemaster E)SWEEP_COUNTER
increments, record:
Something is wrong in the logic for setting metadata registers.
In Vivado 2013.3, critical logic is trimmed (with warning 8232) if any registers are
set from red_pitaya_digdar.v
in a clause like
always @(posedge adc_clk_i) begin
if (adc_rstn_i == 1'b0) begin
trig_count <= 32'h0;
end
end
For now, we're working around this by having Init()
from jbrzusto/ogdar/fpga/fpga.go
set initial values.
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