honkw93 / automatic-verilog Goto Github PK

auto-function may act abnormally when multiple modules in the same file

input [7:0] a,b,c

可以通过有没有drive和load做简单的判断。
另外这个插件真的很棒

RtlTree support `ifdef(recursively)

Suppose I have top.sv and fifo.sv

module top
//submodule
/*autodef*/

  fifo #(
  .DW (ALIGN_FIFO_DW)
) u_align_fifo (
  PORT_LIST
)
endmodule

module fifo#
(
  paramter DW
)
(
  [DW - 1:0] data_in
)

Running autodef should make top.sv

module top
//submodule
/*autodef*/
wire [ALIGN_FIFO_DW - 1:0] data_in;  /********This is correct***********/

  fifo #(
  .DW (ALIGN_FIFO_DW)
) u_align_fifo (
  .data_in( data_in[ALIGN_FIFO_DW - 1:0])
)
endmodule

instead of

module top
//submodule
/*autodef*/
wire [DW - 1:0] data_in;        /********This is wrong***********/

  fifo #(
  .DW (ALIGN_FIFO_DW)
) u_align_fifo (
  .data_in( data_in[DW - 1:0])
)
endmodule

For a register signal declared in the always block, wihich is 4 bits:

After AUTOREG, one 12 bits signal is generated:

The script seems only take the highest bit to generate register bit width.
Actually we should calculate the range between the highest and lowest bit.

Asked by SSS

e.g.
function [7:0] bit_exchange;
input [7:0] bit_in;
input exchange_en;
begin
...
end
endfunction

In sytemverilog, localparam is allowed to show up in the "parameter area, for example

module fifo#
(
  parameter DP = 8,
  localparam PTRW = $clog2(DP)
)
(
  output [PTRW - 1:0] wptr,
  output [PTRW - 1:0] rptr
)

In this condition, localparam should not appear in the instance

请问这个报错是啥意思呢 使用最新版

在运行autoarg时出现的error
，
thanks

经常有这种写法：
module a(
input a
, input b
, input c
, ouput d
);
当模块使用这种写法时，autoinst似乎不能正常的完成，是否能添加这种写法的支持？

"Menu&Mapping 菜单栏和快捷键{{{1
amenu &[email protected]\ @(posedge\ or\ posedge)<TAB><<Leader>al>    :call <SID>AlBpp()<CR>
amenu &[email protected]\ @(posedge\ or\ negedge)                     :call <SID>AlBpn()<CR>
amenu &[email protected]\ @(*)                                        :call <SID>AlB()<CR>
amenu &[email protected]\ @(negedge\ or\ negedge)                     :call <SID>AlBnn()<CR>
amenu &[email protected]\ @(posedge)                                  :call <SID>AlBp()<CR>
amenu &[email protected]\ @(negedge)                                  :call <SID>AlBn()<CR>
amenu &Verilog.Code.Header.AddHeader<TAB><<Leader>hd>                           :call <SID>AddHeader()<CR>
amenu &Verilog.Code.Comment.SingleLineComment<TAB><<Leader>//>                  :call <SID>AutoComment()<CR>
amenu &Verilog.Code.Comment.MultiLineComment<TAB>Visual-Mode\ <<Leader>/*>      <Esc>:call <SID>AutoComment2()<CR>
amenu &Verilog.Code.Comment.CurLineAddComment<TAB><Leader>/$>                   :call <SID>AddCurLineComment()<CR>
if !hasmapto('<Leader>hd')
    nnoremap <Leader>hd                                                 :call <SID>AddHeader()<CR>
endif
if !hasmapto('<Leader>al')
    nnoremap <Leader>al                                                 :call <SID>AlBpp()<CR>
endif
if !hasmapto('<Leader>//','n')
    nnoremap <Leader>//                                                 :call <SID>AutoComment()<CR>
endif
if !hasmapto('<Leader>//','v')
    vnoremap <Leader>//                                                 <Esc>:call <SID>AutoComment2()<CR>
endif
if !hasmapto('<Leader>/e')
    nnoremap <Leader>/e                                                 :call <SID>AddCurLineComment()<CR>
endif

AddCurLineComment() is /e not /$

autodef cannot handle generate and single-bit index correctly

当在IO定义使用input logic [W-1:0] i_data类似的定义，自动例化会例化为
.logici_data(logici_data)

在使用自动例化时（重刷or例化）会例化出.NAL (NAL);的端口，这个是什么问题呢，版本1.5

Document problems may be issued here.

文档问题汇总

1. docsify文档添加英文支持
2. vim文档添加vim-doc
3. 其他文档问题可一并提在此issue下

1. quick always
   easy configuration --> template file

2. quick if
   if begin end

3. global setting change
   close g:att_en automatically
   change g:att_en name

支持filelist嵌套
filelist.f
内部
-f $ROOT/srt/wrap.f

Asked by zxj

improved autowire and autoreg
first add sense for right-hand signal
e.g.
a = {b,c[5:0]};
a <= b+c;
must add sense for b and c

AutoInst修复 `ifdef及 `endif的末尾判断问题

hi，首先感谢作者的插件。我自己替换了一下autoreg和autowire的关键字，做的类似autologic，还有问题。你可以加上system verilog的logic支持吗？ reg和wire不用区分，都用logic代替。

没问题了

RtlTree 优化tags
结构优化
部分窗口异常问题优化

This is what I like to have

The regex used in rtl.vim to match module-inst is ";\s*$", so the following code is not recognized.

mod_a u_a (
    ....
    ); // comment

mod_b u_b (
   ....
   );

mod_c u_c (/*autoinst*/
    ...
   // comment;
   ....
   );

The u_b is not recognized due to comment in last line of u_a. And the u_c is not recognized due to the comment with ";" which generated by autoinst function extracting from mod_c.v .

需要添加非同一行的parameter获取判断
异常例子如下：
module sync
#
(
parameter WIDTH = 1,
parameter RST_VAL = 0,
parameter DLY_STAGE = 2
)
(
input clk,
input rst_n,
input [WIDTH-1:0] i_din,
output reg [WIDTH-1:0] o_dout
);

Asked by gn
e.g.

a u_a1(
. width (width_a[31:0])
);

a u_a2(
. width (width_a[15:0])
);

----->
autodef

wire width_a[15:0]

problem: always choose the last one

asked by JJ
refer to veirlog-mode
e.g.
/* InstName AUTO_TEMPLATE <optional “REGEXP”> (
.sig1 (sigx[@]),
.sig2 (sigy[@”(% (+ 1 @) 4)”]),
);
*/

First of all, I would like to express my gratitude for your outstanding work. This tool has made significant progress compared to many years ago, and it has become more and more useful. I have a few small suggestions, and I hope they can be considered.

1. keep instance comment

.power_on   ( power_on ) ; // my comment info

after instance hope

.power_on   ( power_on ) ; //i,  my comment info

Of course, it is also configurable. let g:atv_autoinst_keep_cmnt = 1

2. INST_NEW dd time

.power_on  ( power_on) ;//i, INST_NEW @2023.04.22 15:03

If the time format is configurable, that would be even better.

3. INST_DEL ' .portxxx( to_xxxxx)' keep old connection information .

INST_DEL not only add port name, but keep old port connection , it's usefull for check the source and destination connection
and the comment of INST_DEL should be keep until user delete by themsevels after confirm, and tools never do that , just keep it is ok.

4. fix $ENV issue

i found the let g:atv_autoinst_add_dir_keep = 1 not work .

//verilog-library-flags:("-v $PROJ_HOME/design/rtl/test.v")

get

//Instance: /proj/sharkl/design/rtl/test.v
test utest(
/*autoinst*/
);

i hope:

//Instance: $PROJ_HOME/design/rtl/test.v

5. inteface support .

Do you have any plans to consider support for SV interface

asked by Shbli
e.g.
module_name #(/autoinstparam/) inst_name(/autoinst/
...
);

when #( and ) in the same line
autokill abnormally killed all lines

plugin文件夹拷贝到～/.vimrc/ 后

代码准备好后，点击Autoinst(1) , 现象如下

该代码使用 :!emacs --batch tb.v -f verilog-batch-auto 是可以正常例化的

autoinst虽然不能使用，但是header功能是可以使用的，好奇怪

asked by Shbli