Type of element is ambiguous in a nested array or record position asignment with concatenation about ghdl HOT 18 CLOSED

I can confirm that I am compiling my code as VHDL-2008. I need to stick to it since the code uses 2008 features in multiple places.

from ghdl.

I think that ghdl is correct according to LRM 9.3.3.3 array types:

For an aggregate of a one-dimensional array type, each choice shall specify values of the index type, and the
expression of each element association shall be of either the element type or the type of the aggregate.

As X"12" & X"34" can be either an std_logic_vector or an array of std_logic_vector (whose type is vector_array), the expression is ambiguous.

Now, if there is a compatibility problem with other tools, I can add a rule (under -frelax) to fix the issue.

from ghdl.

Seems similar to the issue I'm facing currently with the latest GHDL (4.1.0 (4.0.0.r39.g7188e92cf)) compiled with LLVM on Ubuntu 20.04.

I get error: type of element is ambiguous when an array of std_logic_vectors is defined with concatenations present in its elements:

--------------------------------------------------------------------------------------------------------
-- < NOTE: MAX_X and MAX_Y are generics to the entity, defined as positive with values 400. >
--------------------------------------------------------------------------------------------------------
type vector_array_10len_32bit is array (0 to 9) of std_logic_vector(31 downto 0);
constant CFG_DATA : vector_array_10len_32bit := (
        (std_logic_vector(to_unsigned(MAX_Y, 16)) & std_logic_vector(to_unsigned(MAX_X, 16))),
        (x"00000000"),
        (x"00000000"),
        (x"00000000"),
        (x"00000000"),
        (x"00000000"),
        (x"00000000"),
        (x"00000000"),
        (x"00000000"),
        (x"00000000")
);

I was able to circumvent the error by changing the the element definition to:
(std_logic_vector((to_unsigned(MAX_Y, 16)) & (to_unsigned(MAX_X, 16)))).

However, this issue does not come up in Questasim/Vivado and hence a fix would be greatly appreciated to help us avoid changes to our existing source codes. Thank you.

from ghdl.

I fear that ghdl is correct here, but I need to double check with the LRM. This is due to a new feature of vhdl-2008 (and doesn't appear with previous vhdl versions).

from ghdl.

Yeah that should be quite helpful. I assume once that's done we'd just need to add a flag to our ghdl compilation options?

from ghdl.

I didn't realise you can concatenate vectors to form higher dimensional vectors!

Please, if you're happy to use -frelax as a guard for unofficial language extensions that are supported elsewhere, please let this work. I also work with the intersection of Vivado₂₀₀₈∩ModelSim₂₀₀₈, and was dismayed at how pedantic ghdl is!

Does -frelax already exist, or is this going to have to be a new feature? There are a number of issues with the interpretation of others which I'll raise if necessary. Also, to my surprise, ModelSim let me use selected assignment in a sequential context which ghdl didn't like, is it worth flagging that? (Hadn't gotten around to discovering if Vivado supports that.)

from ghdl.