[Bug] GHDL fails to analyze the `mti_util.vhd` ModelSim library file about ghdl HOT 7 CLOSED

15.10 Reserved words

A reserved word shall not be used as an explicitly declared identifier.

5.2.2 Enumeration types
5.2.2.1 General

The identifiers and character literals listed by an enumeration type definition shall be distinct within the enumeration type definition. Each enumeration literal is the declaration of the corresponding enumeration literal. For the purpose of determining the parameter and result type profile of an enumeration literal, this declaration is equivalent to the declaration of a parameterless function whose designator is the same as the enumeration literal and whose result type is the same as the enumeration type; the declaration is, nonetheless, a declaration of a literal, not of a function.

Further the reserved word default can be found in the generic map aspect of an interface package in -2008 or later. That precludes any use if a command line passed flag to discount PSL.

There's also the 'FOREIGN attribute

4.3 Subprogram bodies

A foreign subprogram is one that is decorated with the attribute 'FOREIGN, defined in package STANDARD (see 16.3). The STRING value of the attribute may specify implementation-dependent information about the foreign subprogram. Foreign subprograms may have non-VHDL implementations. An implementation may place restrictions on the appearance of a generic list and a generic map aspect in the declaration of a foreign subprogram. An implementation may also place restrictions on the allowable modes, classes, and types of the formal parameters to a foreign subprogram; such restrictions may include restrictions on the number and allowable order of the parameters.

Excepting foreign subprograms, the algorithm performed by a subprogram is defined by the sequence of statements that appears in the subprogram statement part. For a foreign subprogram, the algorithm performed is implementation defined.

Noting the bit about implementation-dependent information about the foreign subprogram and that the foreign subprogram is implementation (Modelsim) defined.

Now the question is whether or not Modelsim or Vivado analyzes (compiles) this package under 2008 which they clearly should not.

from ghdl.

It seems that one of the errors is that the default keyword is used as a type value here:

type forcetype is (default, deposit, drive, freeze);

I wonder why this is not supported by GHDL?

Because default is a reserved keyword since VHDL-2008. It's used by the integrated PSL language to define the default clock:

default clock is rising_edge(clk);

from ghdl.

@tmeissner Thanks for the explanation. I wonder if there is a way in GHDL to make this error a warning instead?

This is because it seems that ModelSim still compiles the file even when using the reserved keyword, leading to an error instead.

Also in some other VHDL source files we use the reserved word "DEFAULT":

type tDESIGN is (DEFAULT, DESIGN1, DESIGN2, DESIGN3); -- design name

and Vivado is able to compile the file without any problems.

Or, more generally, how could this ModelSim file be compiled with GHDL?

from ghdl.

I'm wondering if there is a way to suppress this error with a flag, or convert it to a warning.

I read there are these flags:

--warn-reserved

-Wreserved

Emit a warning if an identifier is a reserved word in a later VHDL standard.

I'm not sure if those would help, though. What do you think, @tgingold?

nvc, the other VHDL simulator, reports this warning: 'DEFAULT' is a reserved word in VHDL-2008.

from ghdl.

The "shall not" in 15.10 is imperative (mandatory, see 1.3 Structure and terminology of this standard, 1.3.1 General).

The warning is to discourage users analyzing a VHDL design file under a previous revision of the standard from using a reserved word in a later revision of the standard and creating the situation you find yourself in. The idea being part of your tool chain being limited to compliance with an older revision with some possibility the use of a newer affected version of the standard might be possible in the future.

Not all VHDL implementations are capable of mixing libraries or library objects from different revisions of the standard. You could note the prefix for a ghdl .cfg file contains an indication of the VHDL revision of the library it specifies.

Also note the first year in the copyright range in the file shown in your issue predating the -2008 revision.

On top of all that the various calls to FOREIGN subprograms that don't exist in ghdl would preclude functionality should you successfully analyze these files. You'd get those error messages you see in the required subprogram bodies you are required to supply and execute when the FOREIGN subprograms are not made available during elaboration telling you the calls failed.

Without the functionality behind the APIs you'd only be demonstrating those three packages analyze without reaping any benefit for verification.

You could note that the trade secret claims in the file header makes it difficult to reverse engineer the MTI calls behind the package subprograms in some venues because of recent shifts in burden of proof and relaxing duty of care by the trade secret owner. If you don't have clean hands for being exposed to the API you'd be at risk without someone clean room documenting an equivalent API for the package subprograms targeting a distinct VHDL implementation.

Some of the functionality in these packages is also starting to creep into the standard (VHPI, -2019). It may not be worth it to tool developers to pursue for purposes of legacy design portability.

from ghdl.

Thanks for the very detailed and informative reply 👍.

Regarding nvc', it seems that the warning occurs when compiling with the 1993flag. When compiling with2008`, the warning is reported as an error instead.

from ghdl.

You can try to analyze with --std=93 as at that time default was not a reserved identifier.

from ghdl.