Non-synthesizable code leads to latches about ghdl HOT 4 CLOSED

PS: Of course, the line

.PRECIOUS: $(GHDLVERSYNTHOUT)/%.vhd

in the Makefile should read

.PRECIOUS: $(GHDLVERSYNTHOUT)/%.v

from ghdl.

I am not sure to understand the issue. What is the point if the code is not synthesizable ?

from ghdl.

If the code is not synthesizable, it should not create latches, or if it does, ghdl should warn about it. It's just that I've seen this pattern in other's code very often: a fully combinatorial case state with missing assignment for default case. Not that the code is actually not synthesizable, but the non-synthesizable expression for the default case "<= (others => 'X')" fixes the issue, i.e. leads to no latches being inferred. As can be seen by the verilog example, with the yosys' verilog frontend, this is not the case in the first place at all. I think ghdl's behaviour should match.

from ghdl.

Ok. Latches are detected when created by if statement, but not yet by case statement. I am investigating.

from ghdl.