frozen-signal / apple_iie_mmu_iou Goto Github PK

At power-on, POC remains HIGH and RESET_N goes immediately High-Z.
Expected behaviour is:

• POC should remain HIGH for ~2.4 ms, then driven LOW.
• RESET_N should be LOW while POC is HIGH, remain LOW until the video scanner overflows (TC=1), then driven High-Z on the next PHI_1.

Create a document / datasheet describing timings requirements for the IOU and the MMU

Possibly related to #4

Maybe a bus problem that would prevent the CPU to access C03X?

Implementing a hardware solution with the current state of the project is not a trivial task.

This is how the lines are displayed in text mode:

The computation of the memory address for each line is incorrect.

Currently all soft-switches of the IOU are cleared when RESET_N goes LOW.
The correct behaviour is that RESET_N LOW should not change the ITEXT and MIX soft-switches

the MUX RA has changed. Need to update the test.
The test is disabled in the meantime.

The DRAM ICs used by the Apple IIe requires a hold delay on /CAS. Fortunately for the Mainboard's RAM access, the column address is valid until the falling edge of Q3, which is more than enough hold delay.
But for the AUX memory, the column address is strobed on the falling edge of Q3. This may cause a problem because, in the current implementation, that's when ORA0-7 becomes invalid.
So, there might be a race condition for the column address strobe on the AUX DRAM.
Maybe add a delay to make ORA0-7 remain valid a short time past the falling edge of Q3 would make it safer?

Presently all Apple IIc features (VLC HIGH) has been excluded from this implementation.

As of writing, this is what is displayed with a real MMU and a IOU programmed with the sources of this repository:

Check first if there is a problem with LGR/TXT_N or CLRGAT_N.

Presently all Apple IIc features (VLC HIGH) has been excluded from this implementation.

This is what it looks like:

Probably related to #14

As of writing, this is what is displayed with a real MMU and a IOU programmed with the sources of this repository:

Check if there is a bus conflict on RA0-RA7.