Comments (2)
There seems to be a problem with CASEN_N and EN80_N.
This is a logic analyzer capture of the game ALIENS, with a trigger on the falling edge of EN80_N:
Both captures are without a 80-Col Card present, on an enhanced Apple IIe.
With the ASIC MMU:
With the MMU from this repository:
For some reason, the CASEN_N and EN80_N signals are wrong in the prototype.
from apple_iie_mmu_iou.
Fixed in 5f5cba5
At first, I though that the SELMB_N computation of the emulator schematics was incorrect. So, I re-wrote SELMB_N to be closer to the ASIC schematics. This new implementation is much simpler than the other schematics one, but do not fix the problem described above.
Later, I was convinced that PG2 somehow ended up with the wrong value and started searching through the logic analyzer traces until I found this:
The CPU places $C054 on the address bus to reset the soft-switch PG2, But while the address is crumbling, the MMU momentarily sees $C055 and sets it back.
To fix, the latch enabling that control these soft-switches must be forced HIGH during PHI_1 (i.e. during PHI_0 LOW).
This fixes the problem with ALIENS, Apple IIe Diagnostic v2.1, as well as almost every game. Except "The Black Cauldron" that seems to have an problem. Will open a different issue for that one.
from apple_iie_mmu_iou.
Related Issues (19)
- [IOU] At power-on, POC and RESET_N are not valid. HOT 1
- At power-on, the video color burst is present.
- Problem with RAM /RAS hold time. HOT 3
- No familiar 'beep' on power-on
- The computation of the line addresses is incorrect. HOT 1
- Fix the test IOU_TB_SCANNER_MUX HOT 1
- Garbage is displayed when a 64K/80COL card is present HOT 1
- Add a hardware implementation guide HOT 3
- Add Apple IIc features to the IOU
- Add Apple IIc features to the MMU
- HIRES images: rightmost part displayed on the left side, shifted down. HOT 3
- Document all timings requirements for the IOU and MMU
- RESET should not clear the ITEXT and MIX soft-switches. HOT 1
- Check if RA_ENABLE_N need a hold delay HOT 1
- The Black Cauldron has some issues HOT 2
- Bring the signals timings closer to the ASICs HOT 1
- The MMU still seem to have timings issues when used with a RAMWorks III card HOT 1
- RAMWORKS fails to recognize slow RAM in rows other than first. HOT 1
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from apple_iie_mmu_iou.