dvc94ch / pycircuit Goto Github PK

• port directions nturley/netlistsvg#34
• horizontal-vertical selection nturley/netlistsvg#33
• port swapping nturley/netlistsvg#17

• multilayer routing
• assign layer to net
• via clearance
• trace width & trace clearance
• 45-degree routing
• differential length routing
• arbitrary pcb outline

I just came across Netlistsvg which uses Klayjs for rendering Yosys netlists as schematics. Looks like Elkjs is supposed to replace Klayjs. It's a JS port of the Eclipse Layout Kernel. I haven't found any Python implementations yet.

• Output subset of Yosys netlist JSON that Netlistsvg supports
• Make a Netlistsvg SVG skin for common analog components

• Use electro grammar to match components from the Common Parts Library (CPL)
• Export bom as CSV

• port eispice to python3
• add python models for ideal parts
• add support ibis model
• generate testbenches (psu, input-vector)
• add biasing assertions/measurements (v, i, p)
• add assertions in time-domain
• add ac simulation to eispice
• add assertions in frequency-domain
• add CPL part models
• mixed signal simulation with pyhdl

• Add geometry and function information to place file format
• Optimize placement for wirelength
• Support arbitrary pcb outline

Other things to investigate are where and how trace widths etc. should be specified. They currently default to the minimum allowed values from the pcb's TraceDesignRules.

• Packages
• Netlistsvg symbols
• Passives
• Discrete semiconductors
• Opamps
• Electromechanical
• Voltage regulators
• Rest of CPL
• Sifive RISCV mcu's
• Lattice ice40 fpga's
• Arduino, BeagleBoneBlack, RaspberryPi outlines

Arbitrary outlines are mostly supported. The only missing part is a function that takes a shapely polygon and a radius and returns a new shapely polygon with rounded corners.

Save hashes of intermediate files, only rerun placement/routing when hash changes

Hey, I just had my first go at trying to run this. I am assuming it is for python3 as I get SyntaxErrors with python2. So I have done:

virtualenv venv3 -p/usr/bin/python3 && source venv3/bin/activate
pip install . 

When I run the examples from the readme it gives:

Devices

Traceback (most recent call last):
  File "examples/device.py", line 6, in <module>
    Pin('XTAL_XI', Fun('XTAL', 'XI')),
  File "/home/kaspar/projects/pycircuit/venv3/lib/python3.5/site-packages/pycircuit/device.py", line 35, in __init__
    self.bus = Bus.bus_by_type(bus_or_name)
  File "/home/kaspar/projects/pycircuit/venv3/lib/python3.5/site-packages/pycircuit/device.py", line 124, in bus_by_type
    raise IndexError('No Bus with type ' + type)
IndexError: No Bus with type XTAL

Footprints

Traceback (most recent call last):
  File "examples/footprints.py", line 19, in <module>
    Map(17, 'GND'))
  File "/home/kaspar/projects/pycircuit/venv3/lib/python3.5/site-packages/pycircuit/footprint.py", line 36, in __init__
    self.device = Device.device_by_name(device)
  File "/home/kaspar/projects/pycircuit/venv3/lib/python3.5/site-packages/pycircuit/device.py", line 343, in device_by_name
    raise IndexError('No Device with name ' + name)
IndexError: No Device with name MCU

Assign footprints

Traceback (most recent call last):
  File "assign.py", line 3, in <module>
    circuit = top()
NameError: name 'top' is not defined

And I haven run the remaining ones because they seem to require circuit.

• Add buildsystem support (cache optimizer output)
• Add support for constraints (R1 = R2 * 2)
• Add support for impedances
• Add example for sizing a sallen key filter topology
• Add example for sizing a common emitter amplifier

Depends on #21

• Ports have a direction
• Nets are power or signal nets

• Overlay redpitaya measurements and testbench results

Probably best to do this in steps

• Intern qeda generated skin, use interned skin

• Use electrogrammar to search the qeda component library for matches

• Generate the skin, remove interned skin from git

• Add missing symbols to qeda

• Import Package from qeda - remove all package definitions

• Import Devices from qeda - remove all device definitions

• Import Components from qeda - remove all component definitions

See qeda branch for progress

Hello @dvc94ch

I am trying to build this pycircuit the setup installs the pycircuit fine with this command.

pip3 install pycircuit or python3 setup.py install

Am i doing it right can you please help me with how i can install and build and run any example.
I have also tried the electron-lang project but unable to follow any documentation there.
Please let me know.

Regards
Hitesh

• Browser sync support for automatic reloading
• Cross highlighting of nets in netlist and pads / segments in layout
• Usability improvements

• Import a verilog module as a component
• Export arachne pnr pin constraints

Inspired by netlistsvg, a json representation of a pcb should be rendered in svg. Packages should compile to an svg skin file.
Ideally for #2 it is written in JS.

• Export placement constraints into an optimization problem in Z3's smt-lib format

Check pcb with TraceDesignRules and OutlineDesignRules.

In the spirit of pycircuit, making it easier to hack on / modify / replicate electronics some existing projects could be ported. In particular I'd be interested in porting parts of olimex's diy-laptop [0].

[0] https://github.com/OLIMEX/DIY-LAPTOP/tree/master/HARDWARE/A64-TERES

seems annoying. travis ci is missing the python-z3 package that was added in ubuntu-xenial [0] interesting features for guix in the pipeline that might lessen the pain [1]

[0] https://packages.ubuntu.com/search?keywords=python-z3
[1] https://lists.gnu.org/archive/html/guix-devel/2017-11/msg00152.html

Current definition using the python dsl is annoying. Define a hdl inspired language and parse it into our current datastructure.