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pycircuit's Introduction

Build Status

Circuit Description Library

Getting started

common_emitter.py

from pycircuit.circuit import *
from pycircuit.library import *


@circuit('Common Emitter', 'gnd', '12V', 'vin', 'vout')
def common_emitter_amplifer(self, gnd, vcc, vin, vout):
    nb, ne = nets('nb ne')
    Inst('Q', 'npn sot23')['B', 'C', 'E'] = nb, vout, ne

    # Current limiting resistor
    Inst('R', '1.2k')['~', '~'] = vcc, vout

    # Thermal stabilization (leads to a gain reduction)
    Inst('R', '220')['~', '~'] = ne, gnd
    # Shorts Re for AC signal (increases gain)
    Inst('C', '10uF')['~', '~'] = ne, gnd

    # Biasing resistors
    Inst('R', '20k')['~', '~'] = vcc, nb
    Inst('R', '3.6k')['~', '~'] = nb, gnd
    # Decoupling capacitor
    Inst('C', '10uF')['~', '~'] = vin, nb


if __name__ == '__main__':
    from pycircuit.formats import *
    from pycircuit.build import Builder

    Builder(common_emitter_amplifer()).compile()

Schematic

Optimization

sallen_key/build.py

import numpy as np
import scipy.signal as sig
from pycircuit.build import Builder
from pycircuit.circuit import testbench
from pycircuit.optimize import Optimizer

from sallen_key import lp_sallen_key

def lp_optimize():
    spec = sig.butter(2, 2 * np.pi * 100, btype='low', analog=True)
    tb = Builder(testbench(lp_sallen_key())).compile()
    problem = Optimizer(tb, spec)
    cost = problem.optimize()
    print(cost)
    problem.plot_result()
    print(repr(problem.netlist))


if __name__ == '__main__':
    lp_optimize()

After 10s runtime. If it's not good enough run it again... Optimizer

Physical design

joule_thief/build.py

import joule_thief
from pycircuit.build import Builder
from pycircuit.library.design_rules import oshpark_4layer
from placer import Placer
from router import Router
from pykicad.pcb import Zone

def place(filein, fileout):
    placer = Placer()
    placer.place(filein, fileout)


def route(filein, fileout):
    router = Router()
    router.route(filein, fileout)


def post_process(pcb, kpcb):
    xmin, ymin, xmax, ymax = pcb.boundary()
    coords = [(xmin, ymin), (xmin, ymax), (xmax, ymax), (xmax, ymin)]

    zone = Zone(net_name='GND', layer='F.Cu',
                polygon=coords, clearance=0.3)

    kpcb.zones.append(zone)
    return kpcb


if __name__ == '__main__':
    Builder(joule_thief.top(), oshpark_4layer,
            place=place, route=route, post_process=post_process).build()

KiCad

License

ISC License

Copyright (c) 2017, David Craven

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

pycircuit's People

Contributors

dvc94ch avatar kasbah avatar

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pycircuit's Issues

DRC checking

Check pcb with TraceDesignRules and OutlineDesignRules.

Improve placer

  • Add geometry and function information to place file format
  • Optimize placement for wirelength
  • Support arbitrary pcb outline

Use qeda as a component library

Probably best to do this in steps

  • Intern qeda generated skin, use interned skin

  • Use electrogrammar to search the qeda component library for matches

  • Generate the skin, remove interned skin from git

  • Add missing symbols to qeda

  • Import Package from qeda - remove all package definitions

  • Import Devices from qeda - remove all device definitions

  • Import Components from qeda - remove all component definitions

See qeda branch for progress

image

Improve monosat router

  • multilayer routing
  • assign layer to net
  • via clearance
  • trace width & trace clearance
  • 45-degree routing
  • differential length routing
  • arbitrary pcb outline

Add deedgify(polygon, radius) function

Arbitrary outlines are mostly supported. The only missing part is a function that takes a shapely polygon and a radius and returns a new shapely polygon with rounded corners.

Improve circuit optimizer

  • Add buildsystem support (cache optimizer output)
  • Add support for constraints (R1 = R2 * 2)
  • Add support for impedances
  • Add example for sizing a sallen key filter topology
  • Add example for sizing a common emitter amplifier

Depends on #21

Yosys integration

  • Import a verilog module as a component
  • Export arachne pnr pin constraints

Unable to install or use any example.

Hello @dvc94ch

I am trying to build this pycircuit the setup installs the pycircuit fine with this command.

pip3 install pycircuit or python3 setup.py install

Am i doing it right can you please help me with how i can install and build and run any example.
I have also tried the electron-lang project but unable to follow any documentation there.
Please let me know.

Regards
Hitesh

Library: Add all parts from the CPL

  • Packages
  • Netlistsvg symbols
  • Passives
  • Discrete semiconductors
  • Opamps
  • Electromechanical
  • Voltage regulators
  • Rest of CPL
  • Sifive RISCV mcu's
  • Lattice ice40 fpga's
  • Arduino, BeagleBoneBlack, RaspberryPi outlines

Setup and running examples

Hey, I just had my first go at trying to run this. I am assuming it is for python3 as I get SyntaxErrors with python2. So I have done:

virtualenv venv3 -p/usr/bin/python3 && source venv3/bin/activate
pip install . 

When I run the examples from the readme it gives:

Devices

Traceback (most recent call last):
  File "examples/device.py", line 6, in <module>
    Pin('XTAL_XI', Fun('XTAL', 'XI')),
  File "/home/kaspar/projects/pycircuit/venv3/lib/python3.5/site-packages/pycircuit/device.py", line 35, in __init__
    self.bus = Bus.bus_by_type(bus_or_name)
  File "/home/kaspar/projects/pycircuit/venv3/lib/python3.5/site-packages/pycircuit/device.py", line 124, in bus_by_type
    raise IndexError('No Bus with type ' + type)
IndexError: No Bus with type XTAL

Footprints

Traceback (most recent call last):
  File "examples/footprints.py", line 19, in <module>
    Map(17, 'GND'))
  File "/home/kaspar/projects/pycircuit/venv3/lib/python3.5/site-packages/pycircuit/footprint.py", line 36, in __init__
    self.device = Device.device_by_name(device)
  File "/home/kaspar/projects/pycircuit/venv3/lib/python3.5/site-packages/pycircuit/device.py", line 343, in device_by_name
    raise IndexError('No Device with name ' + name)
IndexError: No Device with name MCU

Assign footprints

Traceback (most recent call last):
  File "assign.py", line 3, in <module>
    circuit = top()
NameError: name 'top' is not defined

And I haven run the remaining ones because they seem to require circuit.

Improve simulation support

  • port eispice to python3
  • add python models for ideal parts
  • add support ibis model
  • generate testbenches (psu, input-vector)
  • add biasing assertions/measurements (v, i, p)
  • add assertions in time-domain
  • add ac simulation to eispice
  • add assertions in frequency-domain
  • add CPL part models
  • mixed signal simulation with pyhdl

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