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View Code? Open in Web Editor NEWFull piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
License: GNU General Public License v3.0
Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
License: GNU General Public License v3.0
This implementation seem to be for WIFI standard, I would like to extend it to support DVB-S2 standard. Can you explain the rowPara and pidx matrices? they seem to be indices for routing between CNs and VNs, however I still can't fully map it to the base H-matrix.
Also, if I am not mistaken each colUpdate function takes pointer arguments to arrays of [512], isn't is supposed to be 64?
我最近因为项目需要才开始学ldpc,大概了解到你的这个实现是在解一个全长1536,实际数据1024bit的码,但是十分不明白为什么输入是1536个字节,而输出是1024bit,这样输入不是大了8倍么?这么看来输入应该不是编码后的数据,那么你这个模块实际的输入是什么呢?
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