berkeleylab / marble Goto Github PK

The desired functionality is that the MMC can read the memory supply voltage and in case of incompatible voltages, not turn on the main power supply.

Which Kicad version to use to open the layout?
I have version 6.0.7
When i open the pcb file, all the power planes disappear and it shows ratsnests for all power nets including gnd.
it also gives a message that the file was converted from old version to new.

Import method from Zest design

POE bridge symbols do not match the mounted bridges. Probably it is a KiCad symbol issue.
Quick fix:
Rotate the bridges by 180 degrees.

FPGA

• Capture unique-IDs: FPGA "DNA", Flash "Random number"
• USB: test UART to/from FPGA and microcontroller, program EEPROM
• SPI boot flash: can be programmed, and the FPGA will boot from it;  configure OTP for write-protection
• Write-protect switch: remote readout changes state when actuated, prevents SPI flash programming when activated
• On-board VCXO: measure frequency vs. set value based on absolute pps reference (suggest GPS Pmod)
• Power supplies and their monitoring: read out and cross-check with hand-held voltmeter, exercise both barrel and PoE input, demo switching of FMC +12V power
• DDR3 memory: yes, thorough self-test, FPGA module
• FMC: FMC LPC connectivity can be checked with FMC Carrier Tester; HA and HB banks TBD
• FMC MGT: connectivity can be checked with FMC Carrier Tester
• MGT clock multiplexing: exercise each input and each output
• FMC GBTCLK inputs can be exercised with FMC Carrier Tester

Microcontroller:

• Watchdog the FPGA and its network connection, reset it on timeout
• Monitor temperature and fan speed over I2C
• Manage network settings (MAC and IP address) in EEPROM (user sets them via UART, get transferred to FPGA at boot via SPI)
• Monitor Ethernet PHY via its MDIO
• Set supply voltages over I2C for power-margining tests
• Maintain trust model for un-brickable remote deployment
• Relay JTAG commands to FMC slots

Kintex banks 32 and 33 are HP banks, limited to 1.8V.
This design has them connected to 2.5V supplies.

I discovered this when trying to get an overview of how the FPGA I/O is used:

bank 12: HR 2.5V, FMC2 LA 17-33
bank 13: HR 2.5V, FMC2 HB 00-20
bank 14: HR 2.5V, FMC1 LA 00-16 (plus config)
bank 15: HR 2.5V, FMC1 LA 17-33 (plus RGMII)
bank 16: HR 3.3V, local
bank 32: HP 2.5V, FMC2 HA 00-23
bank 33: HP 2.5V, FMC2 LA 00-16 (plus UART)
bank 34: HP 1.35V, DDR3

TODO:

• Make sure that R147 is DNF
• R309 should be soldered on
• heatsink for U35 (PN: ATS-55170R-C1-R0)
• heatsink for U2 (clock mux)
• change PN for J9 (new PN: 1-2373376-2)

Should be marked as DNF.

Release v1.1 had a Marble-schematic.pdf, but it's missing from later releases. Could we add that?

Also, is there a script to generate that PDF schematic?

Resistors R68 and R69 must be swapped with each other.
9k31 should be connected between OUT and FB, 10k7 should be between FB and GND.

Simulating the ideal diode circuit around Q2 I stumbled across a bit of an issue.

When the input voltage is negative and the ideal diode should be blocking, there is a leakage path through Q1B, R107 and Q1A, shown with red arrow:

This is because emitter - base breakdown voltage of Q1A is only -5V and it sees the full input voltage there when the ideal diode should be blocking.
Leakage current is only limited by R107, so about 17 mA at -24V input (5 mA @ -12V).

... that's maybe a bit too much reverse current through the Q1A base to feel comfortable.

An easy fix would be to put a small (40 V, 0.1 A or so) diode as shown in green.

So far I have launched:

• XR chip and other power supplies
• I can program the microcontroller (after rewiring SWD signals)
  -- I2C PM works and I can communicate with all devices
  -- I2C FPGA also works
  -- I can configure ADN4600
  -- I can read data from INA219s
• FPGA can be programed
• QSFP1 works on 10 GBs with default settings UPDATE: also works with PRBS-31
• QSFP2 (after switching the mux) works on 10 GBs with default settings UPDATE: also works with PRBS-31
• Ethernet works at 1Gb
• FMC1 and FMC2 work

SWD (and JTAG) should be connected to PA13, PA14, and PA15 instead of PC13, PC14, and PC15.

The CLK20_VCXO_T line doesn’t connect to a clock-capable pin. This generates an error when driving an MMCM.

Since we are trying a little to generate xilinx xdc like files from the schematic itself, it would be good to have some signals like FMC names to follow the FMC naming convention (assuming there exists one). Is this legitimate?

https://fmchub.github.io/appendix/VITA57_FMC_HPC_LPC_SIGNALS_AND_PINOUT.html

Looks like some part of the industry goes with this diagram as I see it everywhere. Something to think about.

The pictures were taken when a simple test gateware was running on the FPGA.

See BerkeleyLab/Marble-Mini#54

PN listed in BoM is slightly too wide.
Change to 1-2373376-2.

All capacitors on the clock signals are not soldered in.
Capacitors have an attribute: -standalone but they must be soldered.

Do not plug the main power supply and USB.

Vref for FPGA JTAG is not connected. 2V5 should be connected to pin 2 of J11.

These fixes and improvements have been added in commit 634365b :

1. Some of the power indicator LEDs were lighting when the power rails were disabled. It was fixed by changing the transistor to NMOS.
2. Added more power indicator LEDs: for 3V3_USB and 3V3P
3. I2C was connected to SO-DIMM; SO-DIMM's I2C logic was connected to 3V3P.
4. Changed SI570 power supply to 3V3P.
5. Now U34 and U39 are connected to I2C via a level translator to prevent I2C locking when 3V3 is switched off.
6. R138 was marked as DNF.
7. Fixed issue with PoE bridge diodes (schematic symbol and PCB were changed)
8. Fixed issue with too high LDO output voltage
9. Fixed issue with wrong power indicator LEDs marking.
10. Fixed issue with FMC2 LED.

The level translator should separate 3V3 powered devices from 3V3PM devices.

It's maybe interesting to remove generated files, such as pdfs (Marble_Test_Guide.pdf and Marble_User_guide.pdf), from checked-in files and put them only on each release, as it was done for v1.1.

And we could reference them on README.md and other places in the same way, as it's done now I suppose.

LDO (U47) gets hot during the memory operation. Memory works but it is not good to rely on such hot LDO.
In the new batch, I will add DC/DC converter to power the memory and HP banks.

Solved in commit b1b4e2b

Due to the I2C bus repeaters (U52, U59) latch-up during the power-up procedure JTAG and I2C issues occur.
The solution is to keep the I2C repeater's Enable pin low during power-up.
Proposed reset scheme with D1 and D9 for U52 and U59:

Due to no stock of U47 (TPS7A8901RTJT) voltage regulator, it was not populated. So we now need to provide 1.8 V or 2.0 V to VCCAUX_IO, auxiliary supply voltage.
Solution: Connect C237 (VCCAUX) and C384 (VCCAUXIO2V0).
Picture of layout rendering and rework:

look here

• +12V and GND silkscreen marking on MTA-156 input
• reverse-polarity protection diode on +12V input
• BOM fixes, esp. heat sinks and I2C buffers
• smaller BOM?
• assembly house check for power-plane shorts
• Move test points to PCB connector (e.g. Tag-Connect TC2070; https://www.tag-connect.com/product/tc2070-nl-fp-footprint)
• DNI connectors for SPI and I2C busses (can be soldered on for debugging) (e.g. 609-3692-1-ND)
• Hardware flow control lines RTS/CTS from FT4232H DBUS to MMC
• Swap FPGA_INT and EXP_INT definitions on schematic to be consistent with v1.3
• DNI 0402 resistor between U21 pin 2 (clk) and Gnd. Allows recovery of FTDI chip by temporarily shorting EEPROM clk

They are swapped both in FPGA_MGT schematic and in QSFP1 schematic. It would be less confusing to stick to one place for swapping lanes for readability.