A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
I have read all files of your work.THANKS,it could use in simulink.But When I add to the project in altera meachine.I have some problems.1.the date from camera is yuv format,we write it into fifo stream to sdram and read fifo stream from sdram to your work to encode to h264 format. Then we used the output stream to Network card or serial port to computer to appear the vedio. 2.But when I see your h264topsim.vhd ,it read datas and Arrange into matrices.when datas in intra4*4_DATAI,it was arranged into materices.Should i use another sdram to arrange the datas from camera?THANK for ANSWER.
Hi, I'm trying to implement your IP core into fpga but I'm confused by all the inputs. Does anyone have an example for operating
with an IP core? Thank you.
Dear Sir,
I am trying to run simulation with input yuv at higher resolution (1080p ) and errors popped up and halted simulation like below:
Looking forward to your kind advice on this.
110981 bytes in NAL (28:1 compression) using QP: 28
Framenum: 2 read in ok. Using QP: 28
Warning: VALIDI has fallen when in middle of block
Time: 68083005 ns Iteration: 1 Process: /h264top/xbuffer/line__131 File: C:/Users/swleung/brian/workspace/verilog/4ev/20221005_1737_h264_vhdl/h264_vhdl/h264_vhdl.srcs/sources_1/imports/src/h264buffer.vhd
ERROR: Index 540 out of bound 0 to 539
Time: 68085405 ns Iteration: 1 Process: /h264top/line__1170
File: C:/Users/swleung/brian/workspace/verilog/4ev/20221005_1737_h264_vhdl/h264_vhdl/h264_vhdl.srcs/sim_1/imports/tests/h264topsim.vhd