This repository presents the design and simulation of a Serializer, one of the major components of SerDes which is essentially a parallel in serial out architecture.
- Abstract
- Tools Used
- Serializer
- Reference Circuit
- 2-to-1_Mux
- D-Flip_Flop
- Positive_Latch
- Negative_Latch
- Inverter
- Frequency_Divide_by_2_circuit
- 2-to-1_Serializer
- 8-to-1_Serializer
- Simulations
- Netlist
- Challenges
- Results
- Author
- Acknowledgements
- References
Based on the 2-to-1 Serializer developed, one can use this architecture to implement a multiplexer with a larger number of input channels. Most of them are based on the topology of tree structure. As illustrated in the figure, the tree structure is a natural extension of the 2-to-1 unit, the idea is to group the input channels in pairs and multiplex each pair, reducing the number by a factor of two after each rank. In this architecture, the flip-flop is driven by a clock frequency fck, the serializer in rank 3 is driven by a clock frequency fck/2, in rank 2 are driven by a clock frequency fck/4, and those in the rank1 are driven by a clock frequency fck/8.
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Synopsys Custom Compiler: The Synopsys Custom Compiler™ design environment is a modern solution for full-custom analog, custom digital, and mixed-signal IC design. As the heart of the Synopsys Custom Design Platform, Custom Compiler provides design entry, simulation management and analysis. This tool was used to design the circuit on a transistor level. Steps were followed from the provided doc at Hackathon platform to setup defs file at the following location.
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Synopsys Primewave: PrimeWave™ Design Environment is a comprehensive and flexible environment for simulation setup and analysis of analog, RF, mixed-signal design, custom-digital and memory designs within the Synopsys Custom Design Platform. This tool helped in various types of simulations of the above designed circuit.
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Synopsys 32-28nm SAED_PDK: SAED 32-28nm was used for model library files, and at Typical corner for both p and nMOS (TT).
Serializer Operation
- This figure explains the working of a 2-to-1 serializer, 7 of which are used further ahead for creating the 8-to-1 serializer here.
Serializer 8-to-1
- The pin ordering here is utilized to obtain the serial data in format D1-D2-D3-...-D8. Also, the clock pins are being taken independently, which is made a note of.
- The above two facets facilitated the final implementation.
As Submitted in Literature Survey
- The overall structure here is replicated in the final implementation,but making use of pin-orderings and clock facilitation at each rank as per the figure before it.
This is a transmission-gate based 2:1 mux as seen in "Digital Integrated Circuits" by Prof. Jan Rabaey.
The D-flip flop implementation as a circuit contains a positive and a negative latch, along with inverters and muxes. And thus, consists of sub-circuits which are to be utilized for this design.
This was the first symbol created to test out whether it is possible to just hardcode it at 1.8V without giving an external pin and it worked.
A frequency divide by 2 circuit is created by giving a feedback around at Q negated into the input in a D-FF.
The 2-to-1 Serializer utilized the schematics of sub-circuits rather than symbols just because it saved time.
They are interconnected using the wiring labels rather than congesting it with unnecessary drawing of wiring here.
There was an attempt at utilizing schematics all over for the overall circuit, but that was not easy to navigate and debug as can be seen from above.
Transient Analysis
Reference successfully reproduced
Here, we can see from net1 to the net2 how the data is being serialized out, since the pattern repeats, it has been shown only till 10us.
* Generated for: PrimeSim
* Design library name: Proposed_ckt
* Design cell name: as_8to1
* Design view name: schematic
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09
*Tue Mar 1 18:15:02 2022
.global gnd!
********************************************************************************
* Library : Proposed_ckt
* Cell : as_2to1_serializer
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt as_2to1_serializer clk out din1 din2
xm54 net24 clk net25 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm53 net25 clkb net10 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm52 net9 net25 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm51 net10 net9 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm46 net12 clk net14 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm41 net14 clkb net8 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm42 net7 net14 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm45 net8 net7 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm38 net6 net5 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm37 net5 net12 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm36 net12 clk net6 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm35 din1 clkb net12 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm30 net4 net3 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm29 net3 net24 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm28 net24 clk net4 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm8 din2 clkb net24 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm27 net2 net1 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm24 net1 net17 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm22 net17 clk net2 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm20 net14 clkb net17 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm9 clkb clk vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm1 out clk net25 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm0 out clkb net17 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm50 net24 clkb net25 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm49 net25 clk net10 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm48 net9 net25 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm47 net10 net9 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm39 net12 clkb net14 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm40 net14 clk net8 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm43 net7 net14 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm44 net8 net7 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm34 net6 net5 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm33 net5 net12 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm32 net12 clkb net6 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm31 din1 clk net12 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm7 net4 net3 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm6 net3 net24 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm5 net24 clkb net4 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm2 din2 clk net24 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm26 net2 net1 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm25 net1 net17 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm23 net17 clkb net2 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm21 net14 clk net17 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm3 out clk net17 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm4 out clkb net25 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm10 clkb clk gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
v12 vdd gnd! dc=1.8
.ends as_2to1_serializer
********************************************************************************
* Library : Proposed_ckt
* Cell : as_dff_new
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt as_dff_new clk q din
xm26 net98 q gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm25 q net90 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm23 net90 clkb net98 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm21 net103 clk net90 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm18 net64 net103 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm17 net103 net56 gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm14 net56 clk net64 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm12 din clkb net56 gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm5 clkb clk gnd! gnd! n105 w=0.1u l=0.04u nf=1 m=1
xm27 net98 q vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm24 q net90 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm22 net90 clk net98 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm20 net103 clkb net90 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm19 net64 net103 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm16 net103 net56 vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
xm15 net56 clkb net64 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm11 din clk net56 vdd p105 w=0.15u l=0.04u nf=1 m=1
xm4 clkb clk vdd vdd p105 w=0.15u l=0.04u nf=1 m=1
v8 vdd gnd! dc=1.8
.ends as_dff_new
********************************************************************************
* Library : Proposed_ckt
* Cell : as_8to1_symbol
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt as_8to1_symbol clk clk1 clk2 clk3 out din1 din2 din3 din4 din5 din6 din7
+ din8
xi6 clk1 g e f as_2to1_serializer
xi5 clk2 f c d as_2to1_serializer
xi4 clk2 e a b as_2to1_serializer
xi3 clk3 d din8 din4 as_2to1_serializer
xi2 clk3 c din6 din2 as_2to1_serializer
xi1 clk3 b din7 din3 as_2to1_serializer
xi0 clk3 a din5 din1 as_2to1_serializer
xi7 clk out g as_dff_new
.ends as_8to1_symbol
********************************************************************************
* Library : Proposed_ckt
* Cell : as_8to1
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xi0 0_1 1 2 3 out din1 din2 din3 din4 din5 din6 din7 din8 as_8to1_symbol
v42 din3 gnd! dc=0 pulse ( 0 1.8 7n 0.2n 0.2n 16n 32n )
v44 din5 gnd! dc=0 pulse ( 0 1.8 2n 0.2n 0.2n 16n 32n )
v46 din7 gnd! dc=0 pulse ( 0 1.8 8n 0.2n 0.2n 16n 32n )
v47 din8 gnd! dc=0 pulse ( 0 1.8 8n 0.2n 0.2n 32n 64n )
v43 din4 gnd! dc=0 pulse ( 0 1.8 7n 0.2n 0.2n 32n 64n )
v45 din6 gnd! dc=0 pulse ( 0 1.8 2n 0.2n 0.2n 32n 64n )
v33 din1 gnd! dc=0 pulse ( 0 1.8 3n 0.2n 0.2n 16n 32n )
v41 din2 gnd! dc=0 pulse ( 0 1.8 3n 0.2n 0.2n 32n 64n )
v32 3 gnd! dc=0 pulse ( 0 1.8 0 0.2n 0.2n 8n 16n )
v31 2 gnd! dc=0 pulse ( 0 1.8 0 0.2n 0.2n 4n 8n )
v30 1 gnd! dc=0 pulse ( 0 1.8 0 0.2n 0.2n 2n 4n )
v27 0_1 gnd! dc=0 pulse ( 0 1.8 0 0.2n 0.2n 1n 2n )
.tran '0.1n' '100n' name=tran
.option primesim_remove_probe_prefix = 0
.probe v(*) i(*) level=1
.probe tran v(0_1) v(1) v(2) v(3) v(out) v(din1) v(din2) v(din3) v(din4) v(din5)
+ v(din6) v(din7) v(din8)
.temp 25
.option primesim_output=wdf
.option parhier = LOCAL
.end
As we can see the (W/L)pMOS=(0.15u/0.04u), and (W/L)nMOS=(0.1u/0.04u) is used consistently throughout the design.
- Initially, instead of symbols, the whole circuit consisted of actual schematics instead of their generated symbols. This led to visibility issue as circuit is big. Appropriate symbols were created to facilitate better maneuverablity.
- The frequency divider circuit is yielding latency issues, so as per literature survey, it was concluded that a PLL may be assumed to provide the required clocks at the three ranks respectively, at the same time.
The circuit has been simulated successfully at clock frequency of 500 MHz, and the voltage signal is maintained at 1.8 V throughout, with data input lines transmitting data at 62.5 MHz.
- Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd.
- Synopsys Inc
- IIT Hyderabad
- Analog IC Design Hackathon
- Sameer Durgoji, NIT Karnataka
- Chinmay Panda, IIT Hyderabad
- Assaad, Maher, “Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications. PhD thesis, University of Glasgow, 2009.
- R. Navid et al., "A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology," in IEEE Journal of Solid- State Circuits, April 2015.
- A. A. Suhani S.H., N. Prasad S. and K. S. S. Reddy, "A 20 Gb/s Latency Optimized SerDes Transmitter for Data Centre Applications," IEEE CONECCT, 2020.
- Nivedita Jaiswal, Radheshyam Gamad. "Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers". Circuits and Systems Vol.06 No.03, 2015
- Synopsys Custom Compiler Tutorial by Sameer Durgoji on the Hackathon Platform.
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