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acadvault

A living open-source repository of academic resources for DA-IICT

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

clock_generator

A multiphase clock generator is a requirement for wide band multi-path transmission line filter, amongst other relevant applications. There are various implementations for the same. The chosen one here is functionally adept and is verified post-layout, as well. It is fully digital and hence the number of parameters to be taken care is fairly less compared to its analog counterparts.

common_cells

Common SystemVerilog components

dynamic-charge-sharing-comparator

Input Offset Voltage: ~2 mV • Rise time and Fall time- ~300-750 ns for Vdd = 1.8 V and Vss=-1.8V • Maximum current consumption: ~30uA • Applications: General purpose continuous time comparator • Input Clock frequencies up to 45 kHz

hackathon_iith-snps-vsd_8-to-1_serializer

A Serializer/Deserializer (SerDes pronounced sir-deez or sir-dez) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. A Serializer, one of the major components of SerDes, is a parallel in serial out architecture. For this the generated clock is taken as is, and the focus is not on clock generation, but the serialization aspect.

vsd-iat-fpga

vsd-iat-sign-off-timing-analysis---basics-to-advanced

Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface. The workshop covers all the basic concepts in STA and Timing constraints. It starts with basics of Static Timing Analysis, timing paths, startpoint, endpoint and combinational logic definitions. It explains setup and hold checks, how STA tools calculate setup and hold violations. Then it slowly builds up to cover all aspects of STA like multiple types of timing paths, design rule checks, checks on async pins and clock gates. After that we go into slightly advanced topics like Time borrowing on latches, timing arcs, cell delays and models, impact of clock network on STA. Since STA and timing constraints go hand in hand the workshop covers basics of all the timing constraints that an engineer should know for STA like clock definitions, clock groups, clock characteristics, port delays and timing exceptions. Each day of the workshop is associated with labs so attendees can apply the concepts they have leant that day on practical examples and deepen their knowledge of the concepts.

vsd-synopsys-dc-synthesis-and-sta