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resnet-1k-layers

Deep Residual Networks with 1K Layers

resnet-in-tensorflow

Re-implement Kaiming He's deep residual networks in tensorflow. Can be trained with cifar10.

resnet-on-cifar10

Reimplementation ResNet on cifar10

retinanet

Focal loss for Dense Object Detection

rfnoc-hls-neuralnet

rfsoc-amc

AMC module with Xilinx RF-SoC and two analog front-end mezzanines for SDR and quantum applications

rfsoc_controller

This project implements a controller for driving an optical computer using an FPGA.

rfsoc_qpsk

rfsoc_sam

RFSoC Spectrum Analyser Module on PYNQ

rgbd-slam-tutorial-gx

code for the rgbd-slam tutorial written in cnblogs

risc-v-emulator

简单的RISC-V指令模拟器，实现了绝大多非扩展指令的模拟工作。

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

riscv-sodor

educational microarchitectures for risc-v isa

riscv-test-env

riscv_in_efinix_trion

How to embedded RISCV MCU into Efinix Trion FPGA

riscv_vhdl

VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

ristretto_caffe

ristretto-caffe maintenance by starimpact.

robust_axi_fabric

Generic AXI interconnect fabric

robust_fir

Generic FIR filter

rocket

A web framework for Rust.

rocket-chip

Rocket Chip Generator

rocksdb

A library that provides an embeddable, persistent key-value store for fast storage.

ros

Core ROS packages

roscpp_android

Cross compilation scripts for building ROS nodes using the Android NDK.

rosdep

rosdep multi-package manager system dependency tool

rosetta

Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ

rplidar_ros

rt-thread

RT-Thread is an open source IoT operating system from China.

rtl-sdr

RTL-SDR experimental branch