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dvb-realtek-rtl2832u-2.2.2-10_tuner

Latest RTL2832U driver (full version) with support for 10 tuner

dvb-realtek-rtl2832u-2.2.2-10tuner-mod_kernel-3.0.0

RTL2832U driver modded for Linux kernel 3.0.0

dvb-realtek-rtl2832u-2.2.2-4_tuner

Latest RTL2832U driver (simplified version) with support for only 4 tuner

dvb_tv-aml

dynet

DyNet: The Dynamic Neural Network Toolkit

e-labsimqpsk

e-Labsim二次开发的dll工程，对输入信号进行QPSK调制解调，利用四相松尾环进行载波提取以及同步。

easy-sdr

Creating affordable, easy-to-manufacture prototypes of PCBs to working and expand the capabilities of existing low-cost SDR receivers based on RTL2832U chip.

easyaacencoder

开源项目：简单、高效、稳定的开源音频编码库，支持将各种音频数据(G.711A/PCMA、G.711U/PCMU、G726、PCM)转码成AAC(with adts)格式，其中aac编码部分采用的是业界公认的faac库，EasyAACEncoder支持Windows、Linux、ARM等多种平台，能够广泛应用于各种移动终端设备、嵌入式设备和流媒体转码服务器！

easydarwin

open source、high performance、industrial rtsp streaming server,a lot of optimization on streaming relay,KeyFrame cache,RESTful,and web management,also EasyDarwin support distributed load balancing,a simple streaming media cloud platform architecture.高性能开源RTSP流媒体服务器，基于go语言研发，维护和优化：RTSP推模式转发、RTSP拉模式转发、录像、检索、回放、关键帧缓存、秒开画面、RESTful接口、WEB后台管理、分布式负载均衡，基于EasyDarwin构建出了一套基础的流媒体云视频平台架构！

easyplayer

An elegant, simple, fast android RTSP/RTMP/HLS/HTTP Player.EasyPlayer support RTSP(RTP over TCP/UDP)version & Pro version，cover all kinds of streaming media！EasyPlayer是一款精炼、高效、稳定的流媒体播放器，分为RTSP版和Pro版本，支持各种各样的流媒体音视频播放！

easyplayer_android

An elegant, simple, fast android RTSP/RTMP/HLS/HTTP Player.EasyPlayer support RTSP(RTP over TCP/UDP)version & Pro version，cover all kinds of streaming media！EasyPlayer是一款精炼、高效、稳定的流媒体播放器，分为RTSP版和Pro版本，支持各种各样的流媒体音视频播放！

easypr

An open source project for chinese plate recognition. It aims to be Easy, Flexible, and Accurate. Welcome to contribute your expertise !

easypr_dll_src

EasyPR_Dll all src

easyrtspclient

Streaming media sdk tool：An elegant, simple, high performance & high compatibility RTSP Client Utility,can use in RTSP Player,NVR,RTSP Relay,EasyRTSPClient can run in any platform ,such as x68/x64/Windows/Linux/Android/iOS/arm etc..,with flexible interface,EasyRTSPClient can fit almost all network IPCamera,very easy to use.简单、稳定、高效、易用的RTSPClient工具，支持Windows、Linux、ARM、Android、iOS等几乎所有平台，支持RTP Over TCP/UDP，支持断线重连，能够接入市面上99%以上的IPC，调用简单且成熟稳定！

eblearn

http://eblearn.sourceforge.net/

ecc-x64

Elliptic Curve Cryptography in assembly for linux x64

echarts

A powerful, interactive charting and visualization library for browser

eclipse-class-decompiler

Eclipse Class Decompiler integrates JD, Jad, FernFlower, CFR, Procyon seamlessly with Eclipse and allows Java developers to debug class files without source code directly

egret-3d

Egret Engine 3D API is a high-level 3D framework, it allows developers build cross devices high performance 3D content with WebGL

egret-android-support

egret-android-support

egret-core

Egret is a brand new open mobile game and application engine which allows you to quickly build mobile games and apps on Android,iOS and Windows.

egret-examples

egret-examples

egret-game-library

Egret Game Library

eigen

Git mirror of upstream Mercurial based Eigen repository. The repositories are synced nightly.

elasticsearch

Open Source, Distributed, RESTful Search Engine

elasticsearch-definitive-guide

欢迎加QQ群：109764489，贡献力量！

em070_new-fpga-family-for-cnn-architectures-high-speed-soft-neuron-design

Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventional DSP and multiplier blocks? The optimized hard neuron design will allow all the software and hardware designers to create or test different deep learning network architectures, especially the convolutional neural networks (CNN), more easily and faster in comparing to any previous FPGA family in the market nowadays. The revolutionary idea about this project is to open the gate of creativity for a precise-tailored new generation of FPGA families that can solve the problems of wasting logic resources and/or unneeded buses width as in the conventional DSP blocks nowadays. The project focusing on the anchor point of the any deep learning architecture, which is to design an optimized high-speed neuron block which should replace the conventional DSP blocks to avoid the drawbacks that designers face while trying to fit the CNN architecture design to it. The design of the proposed neuron also takes the parallelism operation concept as it’s primary keystone, beside the minimization of logic elements usage to construct the proposed neuron cell. The targeted neuron design resource usage is not to exceeds 500 ALM and the expected maximum operating frequency of 834.03 MHz for each neuron. In this project, ultra-fast, adaptive, and parallel modules are designed as soft blocks using VHDL code such as parallel Multipliers-Accumulators (MACs), RELU activation function that will contribute to open a new horizon for all the FPGA designers to build their own Convolutional Neural Networks (CNN). We couldn’t stop imagining INTEL ALTERA to lead the market by converting the proposed designed CNN block and to be a part of their new FPGA architecture fabrics in a separated new Logic Family so soon. The users of such proposed CNN blocks will be amazed from the high-speed operation per seconds that it can provide to them while they are trying to design their own CNN architectures. For instance, and according to the first coding trial, the initial speed of just one MAC unit can reach 3.5 Giga Operations per Second (GOPS) and has the ability to multiply up to 4 different inputs beside a common weight value, which will lead to a revolution in the FPGA capabilities for adopting the era of deep learning algorithms especially if we take in our consideration that also the blocks can work in parallel mode which can lead to increasing the data throughput of the proposed project to about 16 Tera Operations per Second (TOPS). Finally, we believe that this proposed CNN block for FPGA is just the first step that will leave no areas for competitions with the conventional CPUs and GPUs due to the massive speed that it can provide and its flexible scalability that it can be achieved from the parallelism concept of operation of such FPGA-based CNN blocks.

emr-code

电子病历系统代码

emvisi2

Background subtraction robust to illumination changes

end-to-end-for-chinese-plate-recognition

多标签分类,端到端的中文车牌识别基于mxnet, End-to-End Chinese plate recognition base on mxnet