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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
AXI总线连接器
synthesizable FFT IP block for FPGA designs
Verilog module for calculation of FFT.
FFT implement by verilog_测试验证已通过
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
WPF写的一个下载小工具,学wpf练手的
OpenCV - 3rdparty
Verilog code for a circuit implementation of Radix-2 FFT
Generic AXI interconnect fabric
uvm AXI BFM(bus functional model)
Verilog AXI components for FPGA implementation
Verilog AXI stream components for FPGA implementation
学习WPF编写的程序集
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