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CVA Open-Source Network-on-Chip Router RTL
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Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University.
All rights reserved.


Overview
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This directory tree contains the source code for the parameterized Network-on-
Chip router RTL developed by the Concurrent VLSI Architecture group at Stanford 
University.

It includes the following subdirectories:

src/      - The actual router implementation.
src/clib/ - A library of generic components used throughout the router.
verif/    - Verification testbenches.

Additional details are provided in [1]; for contact information and 
instructions on how to obtain the most up-to-date version of this code, please 
consult [2].

If you use this code in your research, we would appreciate a citation to [1] in 
any publications to which it has contributed.


References
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[1] Daniel U. Becker. Efficient Microarchitecture for Network-on-Chip Routers. 
    PhD thesis, Stanford University, August 2012.
[2] Enabling Technology for On-Chip Networks. https://nocs.stanford.edu/