My Master Degree Thesis "DESIGN AND VERIFICATION OF DDR SDRAM MEMORY CONTROLLER USING SYSTEMVERILOG FOR HIGHER COVERAGE"

I have uploaded all the related files. please read the certificated and contents Main report and Refrence,

Then Start to look at the code for easy understanding. If you need any help, regarding this. please let me know.

Most of the source code are from the Major MNC companies. I have done the work related to system verilog for verification of the DDR SDRAM. Most of the verilog code is from the source companies. Credit and copyrights goes to them.

For SystemVerilog related coding is my own coding. If you have any queries. please let me know. thanks