'initial begin' bit order vs assigning value on clock cycle about icestorm HOT 2 CLOSED

Thanks a lot for your reply, that makes a lot of sense re. a single clock cycle.

Will close this now.

from icestorm.

You can't access multiple memory cells in a BRAM within the same clock cycle. You need one clock cycle per access. Think about it, how should this work? Your data bus is 64 bit. How could this data bus carry four 64 bit values at the same time?

You can use the (* mem2reg *) attribute for your array definition. Then it is implemented with DFFs, not BRAMs. Then it works in parallel.

Initial block is different. The iCE40 allows the bitstream to contain an initial value for all the BRAMs. This value is written into the BRAM while the FPGA loads its bitstream via SPI during configuration, not during runtime. This is very hardware specific though. Not all FPGAs allow BRAMs to have initial values.

from icestorm.