Not able to use both PLLs of iCE40-HX4K about icestorm HOT 5 CLOSED

You can use two CORE PLLs if you want to. But beware that whenever you use a CORE PLL, the corresponding dedicated PLL input pin becomes reserved and cannot be used as a general purpose input (it can still be used as a general purpose output though).

from icestorm.

TL;DR

You have to pay more attention to Bank 0 and Bank 2 GBIN pins, especially if you want to use PLLs AND use free clock buffer pins as IOs.

Detailed description

If you want to use ice40_PLL_PAD, ice40_PLL_2F_PAD or ice40_PLL_2_PAD you have to route external clock only to:

• IOB_81_GBIN5 - pin 49
• IOT_198_GBIN0 - pin 129

I didn't found that information in any vendor PDF's or pinout files, just figured out it experimentally.

If you want to use ice40_PLL_CORE or ice40_PLL_2F_CORE you won't be able to use PLL dedicated pins as inputs.

Some additional information from iCE40 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02052-1.2):

5.1.2. iCEcube2 Software

* If any instance of PLL is placed in the location of the I/O cell, then, an instance of SB_GB_IO cannot be placed in
that particular I/O cell.

* If an instance of ice40_PLL_CORE or ice40_PLL_2F_CORE is placed, an instance of SB_IO in output-only mode can
be placed in the associated I/O cell location.

* If an instance of ice40_PLL_PAD, ice40_PLL_2F_PAD, ice40_PLL_2_PAD is placed, the associated I/O cell cannot be
used by any SB_IO or SB_GB_IO.

* If an instance of ice40_PLL_2F_CORE, ice40_PLL_2F_PAD, ice40_PLL_2_PAD is placed, an instance of SB_IO in
output-only mode can be placed in the right neighboring I/O cell.

from icestorm.

Pin 128 is not a dedicated PLL input, if you change that to 129 then it works.

from icestorm.

Wow, thanks! I tried to find this information with no success.

Just to be sure. If I use non-dedicated PLL input for clock, I'm able to use the only one CORE PLL and not able to use any PAD type. Right?

from icestorm.

I think I faced exactly the problem you described. What actually inputs pins are dedicated to PLL?
I guess 129 and 49?

I use SB_PLL40_CORE + SB_PLL40_2F_CORE in my project, and nextpnr gives me an error:

Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info:     1128 LCs used as LUT4 only
Info:      507 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info:      312 LCs used as DFF only
Info: Packing carries..
Info:      418 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info:   constrained PLL 'pll1' to X16/Y33/pll_3
ERROR: PLL 'pll2' couldn't be placed anywhere, no suitable BEL found.
ERROR: Packing design failed.
4 warnings, 2 errors
Can't open input file: No such file or directory
Error: Failed to open input file.

In this project almost all IOs are in use, so I can guess that I'm trying to use as in input some PLL related pin.

from icestorm.