This repo includes the effort of me, Yahya Saad, and Abdelhakim Badawy in making a Standard Cell Library (SCL) using Electric VLSI Software. We used a labmda of 180 nm and simulated the delays (PDF and PDR delays) of the gates using SPICE as well. The details can be found in the PDF Report. This course was a part of the Digital Design 2 Course at AUC.
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