Need some explaination for this patch of code about go-pynq HOT 4 OPEN

Hi Yamraj,

As you have figured out, the data processing is happening in the overlay and written back to out_buffer at the allocated location in DDR via DMAs.

You can check the functionality of the overlay by using Xilinx Vivado tool and sourcing the overlay.tcl provided in "spooNN/mnist-cnn/deploy/" location.

Now if you want to change this overlay, the bd can be tweaked by adding another IP or RTL design sources to achieve the processing you need. Once the bd is validated, you can generate a new overlay bitstream. Here are some of the videos which could be of help to generate custom overlays:

https://www.youtube.com/watch?v=UBsCNPWudww&t=398s
https://www.youtube.com/watch?v=LomArt-hi4M

If you do not have access to Xilinx tools, you can think of using existing overlays and building the python software to solve a different problem.

Hope this helps. Let us know if you have further queries.

Cheers!
Radhika

from go-pynq.

@mr-yamraj , If you are just looking for understanding out_buffer computation implemented in the overlay, do look at the source code at:
https://github.com/fpgasystems/spooNN/blob/master/mnist-cnn/hls/mnist-cnn-1W5A.cpp

from go-pynq.

If I just do this by multiplying numpy matrix and applying activation function. Then that will be ineffective right.
What all existing overlays that you can suggest to do the matrix multiplication and other computation.

from go-pynq.

Yes that is the reason this matrix multiply cpp kernel is targeted to Xilinx FPGA to achieve compute efficiency.

You can check for different neural network implementations from pynq community: http://www.pynq.io/community.html

For ex:
QNN overlay from Xilinx labs is here:
https://github.com/Xilinx/QNN-MO-PYNQ/tree/master/qnn/bitstreams/pynqZ1-Z2

from go-pynq.