A project on design of RISC-V processor from RTL specfication to GDS|| generation. Below is the summary of the core.

Core Details:

• core implementing the RISC-V ISA (I- Integer extensions, M- Multiplication and division extension) 2 non maskable interrupt inputs
• 16 kB on-chip PRAM, used as program memory(also used as DRAM for unused locations).
• External bus interface with slave memory for extension of the storage.
• Init-controller for PRAM initializations (copies the machine code from the external memory to internal memory)
• memory-controller controls access to PRAM and the external bus interface based on Memory layout.

• Byte Addressable memory used
• Mapping and access decided in Memory controller
• Core address output 32bits -> Upper 15 bits of the address ignored and rest used as shown below
• SRAM macros were used for these (4 blocks of 4kB each)

Details of the service routines for interrupts and system calls are shown below

• Customised Interface
• Bus Data write and read based on Slave ready.
• Data gets latched once cycle later than all signals
• BUS multiplexing possible.

The design summary is as shown below. For details on the project please refer the report folder ->