Author Name: Mark Johnson
Original Redmine Issue: 268 from https://www.veripool.org
Original Date: 2010-07-09
Original Assignee: Wilson Snyder (@wsnyder)

I believe with the change for emacs error matching, the xemacs code to create creation of verilog-error-regexp-xemacs-alist doesn't work. I made the following change to get it to work for me (xemacs 21.4.17).

;;orig(list 'verilog (mapcar 'cdr verilog-error-regexp-emacs-alist))
(cons 'verilog (mapcar 'cdr verilog-error-regexp-emacs-alist))

Author Name: Albert Lin
Original Redmine Issue: 105 from https://www.veripool.org
Original Date: 2009-07-28
Original Assignee: Michael McNamara

Hi there,

I just downloaded verilog mode 528 and noticed some formatting problems with the assert/cover/assume property statement. Here's code sample:

module myassert(input clk, 
		input reset, 
		input [15:0] data);

    property myproperty;
       @(posedge clk)
	$rose(reset) |-> data == 16'h0;
    endproperty

    //Assert, cover, and assume property statements
    //support begin/end keywords.  The else begin/end
    //clause below is getting indented improperly.
    myassert0: assert property(myproperty) begin
       $display("myassert0 was successful");
    end
else begin
    $fatal("myassert0 was unsuccessful");
end

       //Also, any statements following the assert,
       //cover, and assume property statements get
       // indented too far to the right.
       always @(posedge clk) begin
       end

    
endmodule

As you can see from the sample above, the else begin/end clause of the assert property statement does not get indented. Also, statements following any assert/cover/assume property statements are indented too far to the right.

Author Name: Yoram Stern
Original Redmine Issue: 293 from https://www.veripool.org
Original Date: 2010-10-13
Original Assignee: Wilson Snyder (@wsnyder)

Hi.
When I use /AUTOINPUT/ and /AUTOOUTPUT/ in verilog-2001 style,
I get the ports right, but I want to get also the wires.

For example instead of:

module optchhh ( 
    /*AUTOINPUT*/
    // Beginning of automatic inputs (from unused autoinst inputs)
    input		clk,			// To bb_cpu of bb_cpu.v, ...
    input		bb1,	// To bb_rx_parser of bb_rx_parser.v, ...
    input [2:0]		cc2,	// To bb_rx_parser of bb_rx_parser.v, ...
    // End of automatics
    /*AUTOOUTPUT*/
    // Beginning of automatic outputs (from unused autoinst outputs)
    output		bb2cc1,		// From bb_cpu of bb_cpu.v
    output [1:0]		vv2ccc3_bcount,	// From bb_tx_arbiter of bb_tx_arbiter.v
    // End of automatics
    ) ;

I want to get:

module optchhh ( 
    /*AUTOINPUT*/
    // Beginning of automatic inputs (from unused autoinst inputs)
    input wire		clk,			// To bb_cpu of bb_cpu.v, ...
    input wire		bb1,	// To bb_rx_parser of bb_rx_parser.v, ...
    input wire [2:0]		cc2,	// To bb_rx_parser of bb_rx_parser.v, ...
    // End of automatics
    /*AUTOOUTPUT*/
    // Beginning of automatic outputs (from unused autoinst outputs)
    output wire		bb2cc1,		// From bb_cpu of bb_cpu.v
    output wire [1:0]		vv2ccc3_bcount,	// From bb_tx_arbiter of bb_tx_arbiter.v
    // End of automatics
    ) ;

Is it possible ?
Thanks.

Author Name: David Rogoff
Original Redmine Issue: 75 from https://www.veripool.org
Original Date: 2009-04-05
Original Assignee: Wilson Snyder (@wsnyder)

AUTOs (e.g. AUTOINST, AUTOWIRE) don't work correctly with submodules that contain interface type ports.

Here's a simple case that works:

module submod
     (input wire clk,input wire reset,input wire start, output reg [7:0] count);
endmodule // submod

module top;
    /*AUTOWIRE*/
    submod submod0 (/*AUTOINST*/);
endmodule // top

Now, I add an interface to the ports of submod

interface my_svi;
    logic enable;
    logic error;
    logic [7:0] count2;
    modport master (
                    input enable,
                    output error,
                    output count2);
endinterface // my_svi

module submod
     (my_svi.master my_svi_port,
      input wire clk, input wire reset, input wire start, output reg [7:0] count );
endmodule // submod

module top;
    /*AUTOWIRE*/
    submod submod0 (/*AUTOINST*/);
endmodule // top

When I expand autos, I get this:

interface my_svi;
    logic enable;
    logic error;
    logic [7:0] count2;
    modport master (
                    input enable,
                    output error,
                    output count2);
endinterface // my_svi

module submod
     (my_svi.master my_svi_port,
      input wire clk, input wire reset, input wire start, output reg [7:0] count );
endmodule // submod

module top;
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire [7:0]           count;                  // From submod0 of submod.v
    // End of automatics
    submod submod0 (/*AUTOINST*/
                    // Outputs
                    .count               (count[7:0]),
                    // Inputs
                    .clk                 (clk),
                    .reset               (reset),
                    .start               (start));
endmodule // top

This ignores the interface port. I've run this in more complicated in where auto did really weird stuff, making up wires of random widths! I don't have an example of that here. Anyway, AUTOINST needs to understand and expand interface ports. Also, it would make sense to have an AUTOINTERFACE to go with AUTOWIRE and AUTOREG.

What it should look like is this:

module top;
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire [7:0]           count;                  // From submod0 of submod.v

    /*AUTOINTERFACE*/
    my_svi my_svi_port;  // sdfasdfasdf
        
    // End of automatics
    submod submod0 (/*AUTOINST*/
                    // Interfaces
                    .my_svi_port         (my_svi_port),
                    // Outputs
                    .count               (count[7:0]),
                    // Inputs
                    .clk                 (clk),
                    .reset               (reset),
                    .start               (start));
endmodule // top

Also, do AUTOs understand ports of type logic? Does AUTOWIRE? Should there be an AUTOLOGIC? Isn't SystemVerilog a massive pain with the increased features and complexity? :^)

Thanks,

David

Author Name: David Rogoff
Original Redmine Message: 283 from https://www.veripool.org

Hi guys.

got another one for you. I was going over my key bindings and settings as I finish up moving from xemacs (which I've been using since it was Lucid emacs) to gnu emacs 23 on Linux and Aquamacs on my Mac. I've used the verilog-library-directories for AUTOINST and thought I was using this to jump to source files for instantiated modules using verilog-load-file-at-point. However, I realized today that I've actually just been using find-file-at-point all this time (which I have mapped to c-x, c-f). This worked fine for modules in the same directory.

So, I added ```(define-key verilog-mode-map "\C-x\C-f" 'verilog-load-file-at-point)

I actually wanted to ask you about more advanced features of verilog-load-file-at-point (afterwards referred to as vlfap).  Does it expand shell environment variables like ffap?  This is essential in my environment where we have scripts that set up lots of library and IP paths when entering a cvs sandbox for a project.  ffap handles this, which is great.  I actually just got some great help in gnu.emacs.help.  ffap didn't work if the variable name was inside curly braces.  I got this code that fixes that:

(add-to-list 'ffap-string-at-point-mode-alist
'(file "--:\\$+<>@-Z_[:alpha:]~*?{}" "<@" "@>;.,!:"))

I hope vlfap can support this too.

Thanks,

David

Author Name: Eric Mastromarchi
Original Redmine Issue: 294 from https://www.veripool.org
Original Date: 2010-10-18
Original Assignee: Wilson Snyder (@wsnyder)

verilog-mode v621, with code below I would expect to see dut with an input reg2[3] and a wire created for reg2 as wire reg2[3]

module mod1(input logic [1:0] reg1[4],
             input logic       reg2[3]);
endmodule

module mod2(output logic [1:0] reg1[4]);
endmodule

module dut(/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input                   reg2                   // To foo_i of mod1.v
// End of automatics
            /*AUTOOUTPUT*/
            );
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire [1:0]           reg1;                   // From drv_i of mod2.v
    // End of automatics

    mod1 foo_i(/*AUTOINST*/
               // Inputs
               .reg1                     (reg1[1:0]),
               .reg2                     (reg2));

    /* drv_i AUTO_TEMPLATE (.reg1(reg1[]), );*/
    mod2 drv_i(/*AUTOINST*/
               // Outputs
               .reg1                     (reg1[1:0]));
endmodule

Author Name: Mark Johnson
Original Redmine Issue: 284 from https://www.veripool.org
Original Date: 2010-09-24
Original Assignee: Wilson Snyder (@wsnyder)

The auto stuff seems to work best when the top level is purely structural. I've been in the habit of creating a misc. block to store all the little glue logic snippets, but what I'd really like is just to use Verilog Primitive gates for this. I've thought about prototyping the gates (if 0, module nor (...);...;endmodule;,endif), but seems the primitive gates can only be instantiated positionally.

One other use I can see is when I want to bring a block-to-block wire out as an output. I could just run the signal through the buf primitive and the output would now be unique and be part of the AUTOOUTPUT.

I can always re-create the primitive library in HDL, but would be nice if the verilog-mode could just use the built-in primitives.

Author Name: Clay Douglass
Original Redmine Message: 176 from https://www.veripool.org

I am working with some files that have the port list and input/output declaration in included files e.g.

xunit.ports.v:1:   // Outputs
xunit.ports.v:2:   foo,
xunit.ports.v:3:   // Inputs
xunit.ports.v:4:   bar

xunit.tinc.vs:1:  input bar;
xunit.tinc.vs:2:  output foo;

xunit.v:1:
xunit.v:2:module xunit (
xunit.v:3:`include "xunit.ports.v"
xunit.v:4:)
xunit.v:5:`include "xunit.tinc.vs"
xunit.v:6:  assign foo = bar;
xunit.v:7:endmodule // xunit
xunit.v:8:
xunit.v:9:// Local Variables:
xunit.v:10:// verilog-library-flags:("-y ./ ")
xunit.v:11:// verilog-library-extensions:(".v" ".h" ".sv" ".vs")
xunit.v:12:// eval:(verilog-read-defines)
xunit.v:13:// eval:(verilog-read-includes)
xunit.v:14:// eval:(setq verilog-auto-read-includes t)
xunit.v:15:// End:

xunit_top.v:1:
xunit_top.v:2:module xunit_top ( /*AUTOARG*/)
xunit_top.v:3:  xunit i_xunit(/*AUTOINST*/);
xunit_top.v:4:
xunit_top.v:5:endmodule // xunit_top
xunit_top.v:6:// Local Variables:
xunit_top.v:7:// verilog-library-flags:("-y ./")
xunit_top.v:8:// verilog-library-extensions:(".v" ".h" ".sv" ".vs")
xunit_top.v:9:// eval:(verilog-read-defines)
xunit_top.v:10:// eval:(verilog-read-includes)
xunit_top.v:11:// eval:(setq verilog-auto-read-includes t)
xunit_top.v:12:// End:

If I verilog-auto in xunit_top.v it does nothing. If I manually replace the include with the file content it works fine. Is there a setting to make it follow the `include when it parse for ports?

Thanks,

Clay

Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 296 from https://www.veripool.org
Original Date: 2010-10-20

From: Dan Nicolaescu

One thing that is happening in emacs bzr now is that the mode functions
for programming modes are being changed to use

(define-derived-mode FOO-mode 'prog-mode ... )

The intention is to make all of them inherit from `prog-mode'.

One possible use for this is that one can add to .emacs:

(add-hook 'prog-mode 'flyspell-prog-mode)

and get on the fly spell checking for strings and comments.

Just a heads-up. I don't know how you want to handle this...

Author Name: Mark Johnson
Original Redmine Issue: 272 from https://www.veripool.org
Original Date: 2010-07-22
Original Assignee: Wilson Snyder (@wsnyder)

verilog-pretty-expr prompts for an regular-expression, but quiet was added as a flag.

My fix was to add i\n to the interactive call to skip the quiet flag and correctly set the regexp.

Mark

Author Name: Andreas Olofsson
Original Redmine Issue: 276 from https://www.veripool.org
Original Date: 2010-08-05

My apologies if there is an easy way to do this already, but I couldn't find one, so I am adding this as a feature request. I am trying to insert a piece of text from a file in every file in our design and I want to make sure the text can be automatically updated every time I press C-c,C-a in a file.

I tried the following, but it inserts the text every time I do the c-a magic.

/AUTOINSERTLISP(insert (shell-command-to-string "cat copyright.txt"))/

Maybe this goes against the idea of emacs mode and is more along the line of a vpp, but I thought I would check.

Author Name: Shankar Giri
Original Redmine Issue: 203 from https://www.veripool.org
Original Date: 2010-01-13
Original Assignee: Michael McNamara

Noticed that while ifdef, else and endif indents properly, elsif did not. Hence modified verilog-mode.el to support `elsif indentation. Patch attached.

Author Name: Scott Roland
Original Redmine Issue: 271 from https://www.veripool.org
Original Date: 2010-07-21

Here is a collection of indentation issues I see with Revision 629

// This is an example file to show the indentation errors I see with
// the verilog-mode.

// The assumption is that this file will be included into another
// file defining a module.

initial begin
    int unsigned count = 0;
    int value; // ERROR #1: value should align with count
    string source_str;
end

    task begin_trans // ERROR #2 task should align with end
      (input int h_stream ///<[in ] Handle of the stream to use
       );
    endtask : begin_trans

    //////////////////////////////////////////////////////////////////////
        // ERROR #3 Doxygen inline comment should not cause this indent

Author Name: Chakradhara Aradhyula
Original Redmine Issue: 250 from https://www.veripool.org
Original Date: 2010-04-27
Original Assignee: Wilson Snyder (@wsnyder)

This problem happens, when I use emacs. It works with xemacs.

I attached the tar file with example.
EMACS Version:
GNU Emacs 23.1.1 (x86_64-unknown-linux-gnu, GTK+ Version 2.10.4)
Verilog-made: version 605.

Any Idea?

Author Name: Brad Dobbie
Original Redmine Issue: 242 from https://www.veripool.org
Original Date: 2010-04-15
Original Assignee: Wilson Snyder (@wsnyder)

I like how Verilog-Mode lets you middle-click on a `include file, and it brings up that file in a buffer.

`include "mod_include.v"

I was wondering if there was a way to do the same thing for AUTOINST module instantiations. It seems like it could be possible, since you are already processing the file to get its ports, etc. This would be a good way to traverse hierarchy and browse a design.

    mod_inst1 inst1
      (/*AUTOINST*/
       // Outputs
       ......

I'd like to be able to click on "mod_inst1" and have it open that file in a new buffer.

Author Name: Chakradhara Aradhyula
Original Redmine Message: 270 from https://www.veripool.org

It is not able to find module, if the module is instantiated as follows:
//Non-working code
lower_cell lower_cell_1 // write
(/AUTOINST/
);

//Working code
lower_cell lower_cell_1 //
(/AUTOINST/
);

Same thing works with 587 verilog-mode version.

Please check this one.

Author Name: Pierre-David Pfister
Original Redmine Issue: 305 from https://www.veripool.org
Original Date: 2010-11-24
Original Assignee: Wilson Snyder (@wsnyder)

Hi,

I don't want verilog-mode to auto lineup my ANSI-style input/output declarations. I have tried:

(setq verilog-auto-lineup nil)

I have had this line in my .emacs for a long time, but it looks like the newer modes ignore this setting (I have updated to 655). E.g. when I have a declaration like the following:

module test
  (
    input  logic a,
    input  logic [3:0] b,
    output logic c,
    output logic d
    );
endmodule

and try to add a line, say after input the 'b' input declaration, I type and all the declarations get lined-up (which I don't want). Is this a bug or am I doing something wrong?
I didn't notice this in versions earlier than a month or two ago...

Thanks,

Pierre

Author Name: Alan Morgan
Original Redmine Issue: 104 from https://www.veripool.org
Original Date: 2009-07-28
Original Assignee: Michael McNamara

I've recently moved from using old Verilog Mode v357 to v528. Immediately I have noticed that the code indenting no longer works as it used to. This may be a deliberate change, but personally I preferred the old way and can't see any advantage to it, so I think this change is a bug.

So here's an example of what I'm talking about. I just started a new module, and the first few lines of code look like this:

module soft_rst
  (
    // System clock and reset
     input           clk,
     input           rst_n,
    
    // Interface to software land
     input           req_soft_rst,   // Soft reset request
     output          soft_rst_dne,   // Soft reset done

    // Interface to other modules
     output          dma_halt,       // Reset pending, halt activity
     input           tx_quiet,       // TX side is dormant
     input           rx_quiet,       // RX side is dormant
     output       soft_rst,       // Soft (sync) reset to VC3 side
     output       hs_async_rst_n  // Async reset to host side
    );

    reg [1:0]     state;

    localparam [1:0] IDLE = 2'h0,
      HALT = 2'h1,
      RST  = 2'h2,
      DONE = 2'h3;
    
endmodule // soft_rst

Notice that the last two output assignments and the last three localparams aren't aligned with the declarations above. If I run indent-region on this (C-M-), or equivalently press TAB the lines that aren't yet aligned, in Verilog mode v357 it turns into this:

module soft_rst
  (
    // System clock and reset
     input           clk,
     input           rst_n,
  
    // Interface to software land
     input           req_soft_rst,   // Soft reset request
     output          soft_rst_dne,   // Soft reset done

    // Interface to other modules
     output          dma_halt,       // Reset pending, halt activity
     input           tx_quiet,       // TX side is dormant
     input           rx_quiet,       // RX side is dormant
     output          soft_rst,       // Soft (sync) reset to VC3 side
     output          hs_async_rst_n  // Async reset to host side
    );

    reg [1:0]        state;

    localparam [1:0] IDLE = 2'h0,
                     HALT = 2'h1,
                     RST  = 2'h2,
                     DONE = 2'h3;
    
endmodule // soft_rst

but in v528 it doesn't.

I've tried this in a vanilla emacs (-no_init_file -no-site-file) and the result is the same.

Emacs : GNU Emacs 21.3.1 (x86_64-unknown-linux-gnu, X toolkit, Xaw3d scroll bars)
of 2006-09-26 on mon-irva-35

Thanks for Verilog Mode!

Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 270 from https://www.veripool.org
Original Date: 2010-07-19
Original Assignee: Wilson Snyder (@wsnyder)

See http://www.veripool.org/boards/15/topics/show/315-Verilog-mode-AUTOINST-and-SystemVerilog-interfaces

Author Name: Marc LAURENT
Original Redmine Issue: 77 from https://www.veripool.org
Original Date: 2009-04-07
Original Assignee: Wilson Snyder (@wsnyder)

According to http://www.veripool.org/wiki/verilog-mode/verilog-mode_veritedium#SEC17, "The @ will be replaced by the last digits in the instantiation's name."

But in fact it is currently replaced by the first digits in the instantiation's name.

It seems to me that just adding a $ at the end of the tpl-regexp expression in verilog-read-auto-template on line 7073 would correct the issue.

(let ((tpl-regexp "\([0-9]+\)$")

Best regards,

Marc LAURENT

Author Name: Robert Swan
Original Redmine Message: 327 from https://www.veripool.org

Would be great if I could keep underscore as a word boundary, so that forward-word, backwards-word, delete-word etc. would work the same as in c++-mode. I tried removing the line

 (modify-syntax-entry ?_ "w" table) 

but then syntax highlighting goes wrong.

Robert

Author Name: Chakradhara Aradhyula
Original Redmine Issue: 303 from https://www.veripool.org
Original Date: 2010-11-11
Original Assignee: Wilson Snyder (@wsnyder)

I cretaed small example to reproduce this problem.
I attached the file with this example.

Module A:
module A(/*AUTOARG*/
    // Outputs
    SIG_NAMEA
    );
output [224*1-1:128*1] SIG_NAMEA;
//output [223:128] SIG_NAMEA;
endmodule

Module B:
module B(/*AUTOARG*/
    // Outputs
    SIG_NAMEA
    );
  output [127:0]                        SIG_NAMEA;
endmodule

Module TOP:
module TOP (/*AUTOARG*/
    // Outputs
    SIG_NAMEA
    )
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [224*1-1:128*1]  SIG_NAMEA;              // From A of A.v, ..., Couldn't Merge
// End of automatics
/*AUTOINPUT*/
/*AUTOWIRE*/

A A(/*AUTOINST*/
     // Outputs
     .SIG_NAMEA                          (SIG_NAMEA[224*1-1:128*1]));
B B(/*AUTOINST*/
     // Outputs
     .SIG_NAMEA                          (SIG_NAMEA[127:0]));
endmodule

Author Name: Joachim Lechner
Original Redmine Issue: 259 from https://www.veripool.org
Original Date: 2010-06-04
Original Assignee: Wilson Snyder (@wsnyder)

In the attached files the verilogmode adds AUTOARG within a task.
It seems to me that the comment string is parsed.
If it is changed then nothing is added?!

Best Regards, Joachim

PS:
xemacs [version 21.4.15; November 2008]
RedHat Desktop Release 4, 2.6.9-89.0.23.ELsmp #1 SMP x86_64 GNU/Linux
verilog-mode: r624 (same problem occurs in previous versions !)

Author Name: Steve Pearlmutter
Original Redmine Issue: 258 from https://www.veripool.org
Original Date: 2010-06-02
Original Assignee: Michael McNamara

In v624:

Another SystemVerilog syntax. Hit return after "endtask" to create the endcomment, which will say "automatic".

task automatic blah();
endtask

Author Name: jeff steele (@jsteele22)
Original Redmine Message: 137 from https://www.veripool.org

Hi,

I'm trying to use Verilog-2001 style (* *) constraints, but the indentation gets screwed up.
I'm using verilog-mode.el version 502

module example(out1, out2, out3);

    (* LOC = "D14" *)
  output 	     out1;
    (* LOC = "C15" *)
     output 	     out2;
    (* LOC = "C16" *)
       output 	     out3;
    

    out1 = 1'b1;
    out2 = 1'b1;
    out3 = 1'b1;
endmodule

Is there some way to make this work ?

Author Name: Pierre-David Pfister
Original Redmine Issue: 290 from https://www.veripool.org
Original Date: 2010-09-30
Original Assignee: Michael McNamara

Hi,
The Verilog-mode adds an extra indentation after import of DPI-C function:

module toto (input logic dummy);
  import "DPI-C" pure function real fabs (input real a);
     logic a; // wrong indentation
     endmodule // wrong indentation

Thanks,
Pierre

Author Name: Luis Gutierrez
Original Redmine Message: 315 from https://www.veripool.org

Hi, I've searched the docs and the wiki, but I can't figure out how to AUOTINST to a SV interface.

For example, given the following code:

------------------------------ my_sv_if.sv --------------------------------
interface my_sv_if
  logic a;
  logic b;
  modport master_mp(input a, output b);
  modport slave_mp(output a, input b);
  modport monitor (input a, input b);
endinterface

-------------------------------- my_tb.sv ---------------------------------
module my_tb;
  my_if inst_if (/*AUTOINST*/);
endmodule

---------------------------------------------------------------------------

verilog-mode will complain with the following error:

"verilog-modi-lookup: biu_tb.v:738: Can't locate my_if module definition
     Check the verilog-library-directories variable.
     I looked in (if not listed, doesn't exist):
	< some path >
	< some path /my_if.sv >"

What is very weird is that if I change the declaration from declaration of my_sv.sv from 'interface' to module, then verilog-mode correctly maps the first port of the interface.

Am I missing something syntax wide to interface properly (ie, modport name/usage?), or are interfaces currently not supported?

Thanks in advance,

Luis Gutierrez

PS. I'm using version 629 of verilog-mode.

Author Name: Pierre-David Pfister
Original Redmine Issue: 195 from https://www.veripool.org
Original Date: 2009-12-04
Original Assignee: Wilson Snyder (@wsnyder)

Hi,
AUTOWIRE does not add undeclared wires for output ports with a type defined in a SystemVerilog package (see the attached testcase code). In that testcase, the signal 'sub_enum' is not declared by AUTOWIRE.
Thanks,
Pierre

Author Name: Tony Keiser
Original Redmine Issue: 273 from https://www.veripool.org
Original Date: 2010-07-27
Original Assignee: Michael McNamara

I have noticed an indentation problem in verilog-mode v.631 on emacs 23.1 and 23.2 when using this particular style to
define and set default values for module parameters. The OS is Windows 7 64-bit.

module ui_wr_data #
  (
  parameter TCQ = 100,
		parameter APP_DATA_WIDTH       = 256,
			parameter APP_MASK_WIDTH       = 32,
				parameter ECC                  = "OFF",
					parameter ECC_TEST             = "OFF",
						parameter CWL                  = 5
																						 )
	(/*AUTOARG*/
																						 // Outputs
																						 app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
							raw_not_ecc,
							// Inputs
							rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
							app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
							ram_init_done_r, ram_init_addr
																						 );

Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 218 from https://www.veripool.org
Original Date: 2010-02-19
Original Assignee: Michael McNamara

pure virtual functions indent wrong, because they don't have endfunctions (yuk, I know).

// pure virtual functions have no endfunction.
virtual class pure_virt_func_class;
    pure virtual function string pure_virt_func();
       pure virtual function string pure_virt_func();
          pure virtual function string pure_virt_func();
          endclass

Author Name: Kevin Heilman
Original Redmine Issue: 292 from https://www.veripool.org
Original Date: 2010-10-12
Original Assignee: Wilson Snyder (@wsnyder)

If SV function and task definitions are made outside the class declaration, the endfunction comment is created correctly but the endtask comment is the name of the class rather than the name of the task. For example:

function class_name::func_name();
  begin
  end
endfunction // func_name

task class_name::task_name();
  begin
  end
endtask // class_name

By trial and error I hacked in what appears to be a fix to version 646:

diff verilog-mode.el-646 verilog-mode.el-646-modified 
4237c4237,4239
< 		    (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
---
> 		    (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
> 		    (setq name-re "\\w+\\s-*(")
>         )

Using the modified code produces

endtask // task_name

for the end comment on the task definition.

Author Name: Kev Pet
Original Redmine Issue: 279 from https://www.veripool.org
Original Date: 2010-08-18

When a constraint block contains foreach or if statements, auto-indent does not work

constraint PortCfg::SubportSpeedCnstr
  {
    solve subportCnt before subportSpeedArr;
    subportSpeedArr.size == subportCnt;

    foreach(subportSpeedArr[i])
    {
     if(subportMode == SP10X)
     {
    subportSpeedArr[i] inside {SP1G,SP10G};
}
     }
    }

Author Name: Alon Rachmani
Original Redmine Message: 169 from https://www.veripool.org

Hi
I am trying to use verilog-mode for verilog 2001 ansi-style input. When I add the AUTOINPUT,AUTOOUTPUT in the module parenthesis as mentioned in the FAQ below.
“How do I use Verilog 2001 style port lists?
Place AUTOINPUT/AUTOOUTPUT etc inside the module () parenthesis.�

The outcome is verilog 95 style in the parenthesis. As far as I understood I need to set the verilog-mode-v2k parameter somewhere in the init.el.
How do I add this and in which file to make the AUTO understand that a want verilog 2001 syntax?
Regard
Alon

Author Name: Pierre-David Pfister
Original Redmine Issue: 286 from https://www.veripool.org

Hi,
Classes are not indented when declared in a package.

package toto;
class titi;
endclass
endpackage

Should rather be, in my opinion:

package toto;
class titi;
endclass
endpackage

Thanks,
Pierre

I'm using version 639 of Verilog mode.

Author Name: Yoram Stern
Original Redmine Issue: 74 from https://www.veripool.org
Original Date: 2009-04-02
Original Assignee: Wilson Snyder (@wsnyder)

Hi.
I have a piece of code that looks like that:

module blabla_wrapper();
/AUTOWIRE/
blablock blablock (/AUTOINST/);
endmodule

Now the /AUTOWIRE/ does not generate wire statements to inputs of my blablock.
Do you have a directive to generate wires to unconnected inputs of an instantiation ?
Thanks.

Author Name: Jan Frode Lønnum
Original Redmine Issue: 287 from https://www.veripool.org
Original Date: 2010-09-27
Original Assignee: Wilson Snyder (@wsnyder)

First of all, thank you for an excellent package.

I use an IP which is something like this:

module Ptest #(
parameter I_CONTROL = 8'h 00, R_CONTROL = 8'h00)
(
input scanTest,
input scanArst);

endmodule

When I instantiate I get:

Ptest
#(/AUTOINSTPARAM/
// Parameters
.I_CONTROL (I_CONTROL)) u_Ptest
(
/AUTOINST/
// Interfaces
.00 (00),
.R_CONTROL (R_CONTROL),
// Inputs
.scanTest (scanTest),
.scanArst (scanArst));

I think the problem is the space in the default value of the parameter I_CONTROL

Author Name: Lane Brooks
Original Redmine Issue: 82 from https://www.veripool.org
Original Date: 2009-05-02
Original Assignee: Wilson Snyder (@wsnyder)

Auto mode incorrectly deletes the comma after the a in the following verilog code:

module top
  (input [`WIDTH:0] a, /* This comma gets deleted */
    /*AUTOOUTPUT*/
    /*AUTOINPUT*/
    );

    child child(/*AUTOINST*/);

endmodule

module child(input b);
endmodule

It the preprocesser WIDTH</code> that causes the problem. If <code>WIDTH is made a constant, then the comma does not get deleted.

Author Name: Matthew Lovell
Original Redmine Issue: 281 from https://www.veripool.org
Original Date: 2010-09-09
Original Assignee: Wilson Snyder (@wsnyder)

I've defined a SystemVerilog module as follows:

import my_type_definitions::*;

module my_module
 (

 // Packed arrays of packed structs
 output binding_info_t   [NUM_BINDINGS-1:0] bind_info,
 output binding_decode_t [NUM_BINDINGS-1:0] bind_decode

 );

 ...

When the parent attempts to auto-instantiate this module, that instance ends up getting 4 ports due to the above outputs, rather than the 2 I would have expected:

.binding_info_t      (binding_info_t),
.bind_info           (bind_info),
.binding_decode_t    (binding_decode_t),
.bind_decode         (bind_decode),

It appears as if the non-standard data type of the ports is getting picked up as the port name.

This occurs with verilog-mode version 621 running under XEmacs 21.5

Author Name: Peter Stroud
Original Redmine Issue: 295 from https://www.veripool.org
Original Date: 2010-10-18
Original Assignee: Wilson Snyder (@wsnyder)

Hello.
I've noticed that AUTOWIRE does not create a wire when an assign statement to an interface with the same wire name exists. Example below using verilog-version 638 in xemacs.
Thanks,
-Peter

interface my_interface ();
    logic [2:0] out2;
    logic [2:0] out3;
endinterface: my_interface

module foobar (input [2:0] in2,output [2:0] out2);
endmodule

module foo_autowire_fails (my_interface itf);
    /*AUTOWIRE*/
    assign itf.out2 = out2; // perhaps a namespace collision?
    foobar foobar0
      (/*AUTOINST*/
       // Outputs
       .out2				(out2[2:0]),
       // Inputs
       .in2				(in2[2:0]));
endmodule   

module foo_autowire_works (my_interface itf);
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire [2:0]		out2;			// From foobar0 of foobar.v
    // End of automatics
    assign itf.out3 = out2;
    foobar foobar0
      (/*AUTOINST*/
       // Outputs
       .out2				(out2[2:0]),
       // Inputs
       .in2				(in2[2:0]));
endmodule

Author Name: Dan Dever
Original Redmine Issue: 190 from https://www.veripool.org
Original Date: 2009-11-18
Original Assignee: Michael McNamara

I'm using verilog-mode 1.14.

Indentation differs before and after an always block. Before the block, a multi-line wire initialization is indented to align with the wire name (which I like). After the always block, the indentation is to just after the equals sign:

module foo ();
    // Before the always block,
    // indents to here: (which I like)
    //          V
    wire [10:0] mux_output0 =
                select0[0] ? mux_input0 :
                select0[1] ? mux_input1 :
                select0[2] ? mux_input2 :
                select0[3] ? mux_input3 :
                select0[4] ? mux_input4 :
                select0[5] ? mux_input5 :
                select0[6] ? mux_input6 :
                mux_input7;
                
    reg foobar;
    always @(posedge clk)
      if (reset_n) begin
         foobar <= 1'b0;
      end
    
    // After the always block,
    // indents to here:
    //                       V
    wire [10:0] mux_output1 =
                             select1[0] ? mux_input8 :
                             select1[1] ? mux_input9 :
                             select1[2] ? mux_input10 :
                             select1[3] ? mux_input11 :
                             select1[4] ? mux_input12 :
                             select1[5] ? mux_input13 :
                             select1[6] ? mux_input14 :
                             mux_input15;
endmodule

Author Name: Jan Frode Lønnum
Original Redmine Issue: 302 from https://www.veripool.org
Original Date: 2010-11-10
Original Assignee: Wilson Snyder (@wsnyder)

Hi,

I have a small testcase:

module Abc
  #(
  parameter No1 = 6,
  parameter int unsigned No2                                                  // Parameter no. 2
                        = pa_Abc::No2,
  parameter bit          No3 [No1:0][No2-1:0]                                 // Parameter no. 3
                        = pa_Abc::No3
  )

  (
  input  logic ck,
  input  logic [No1-1:0][31:0] abc
  input  logic [No1-1:0][31:0] abc

  );

endmodule   

and after instantiating this I get:

  Abc #(/*AUTOINSTPARAM*/
         // Parameters
         .No1                            (No1),
         .No3                            (No3)) u_Abc
  (
    /*AUTOINST*/
    // Interfaces
    .No2                                 (No2),
    // Inputs
    .ck                                  (ck),
    .abc                                 (abc/*[No1-1:0][31:0]*/));

I think it is "unsigned" that is the problem for parameter no. 2.
Is it possible to have the abc input instantiated as an array?

Best Regards,
Jan Frode Lønnum

Author Name: Gary Delp
Original Redmine Issue: 269 from https://www.veripool.org
Original Date: 2010-07-14
Original Assignee: Wilson Snyder (@wsnyder)

If you would consider folding this in, that would be great.

*** verilog-mode.el	2010-07-14 17:29:54.201890000 -0500
--- -	2010-07-14 17:34:41.068421000 -0500
***************
*** 1017,1022 ****
--- 1017,1029 ----
     :type 'string)
  (put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp)
  
+ (defcustom verilog-auto-tieoff-ignore-regexp nil
+   "*If set, when creating AUTOTIEOFF list, ignore signals matching this regexp.
+ See the \\[verilog-faq] for examples on using this."
+   :group 'verilog-mode-auto
+   :type 'string)
+ (put 'verilog-auto-tieoff-ignore-regexp 'safe-local-variable 'stringp)
+ 
  (defcustom verilog-typedef-regexp nil
     "*If non-nil, regular expression that matches Verilog-2001 typedef names.
  For example, \"_t$\" matches typedefs named with _t, as in the C language."
***************
*** 10821,10826 ****
--- 10828,10836 ----
  Signals that match `verilog-active-low-regexp' will be deasserted by tieing
  them to a one.
  
+ You can add signals you do not want included in AUTOTIEOFF with
+ `verilog-auto-tieoff-ignore-regexp'.
+ 
  An example of making a stub for another module:
  
       module ExampStub (/*AUTOINST*/);
***************
*** 10863,10868 ****
--- 10873,10880 ----
  			      (verilog-decls-get-gparams moddecls)
  			      (verilog-subdecls-get-outputs modsubdecls)
  			      (verilog-subdecls-get-inouts modsubdecls)))))
+       (setq sig-list (verilog-signals-not-matching-regexp
+ 		      sig-list verilog-auto-tieoff-ignore-regexp))
         (when sig-list
  	(forward-line 1)
  	(verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")

Author Name: Michael Laajanen
Original Redmine Issue: 264 from https://www.veripool.org
Original Date: 2010-06-13
Original Assignee: Wilson Snyder (@wsnyder)

Single char signals does not get "blue", such as the 'q' below

//
// ingress FIFO
//
pcm_fifo i_fifo_i1(
						 .aclr(aclk),
						 .data(sample),
						 .rdclk(clk),
						 .rdreq(i_fifo_rd),
						 .wrclk(clk),
						 .wrreq(i_fifo_we),
						 .q(pcm_dib),
						 .rdempty(i_fifo_ef),
						 .wrfull(i_fifo_ff),
						 .wrusedw(i_fifo_wrusedw)
						 );

Emacs : GNU Emacs 22.2.1 (i386-pc-solaris2.10, Motif Version 2.1.0)
of 2008-08-24 on giulia
Package: verilog-mode v616

current state:

(setq
verilog-active-low-regexp nil
verilog-align-ifelse nil
verilog-assignment-delay ""
verilog-auto-arg-sort nil
verilog-auto-endcomments t
verilog-auto-hook nil
verilog-auto-ignore-concat nil
verilog-auto-indent-on-newline t
verilog-auto-inout-ignore-regexp nil
verilog-auto-input-ignore-regexp nil
verilog-auto-inst-column 40
verilog-auto-inst-dot-name nil
verilog-auto-inst-param-value nil
verilog-auto-inst-template-numbers nil
verilog-auto-inst-vector t
verilog-auto-lineup '(all)
verilog-auto-newline t
verilog-auto-output-ignore-regexp nil
verilog-auto-read-includes nil
verilog-auto-reset-widths t
verilog-auto-save-policy nil
verilog-auto-sense-defines-constant nil
verilog-auto-sense-include-inputs nil
verilog-auto-star-expand t
verilog-auto-star-save nil
verilog-auto-unused-ignore-regexp nil
verilog-before-auto-hook nil
verilog-before-delete-auto-hook nil
verilog-before-getopt-flags-hook nil
verilog-case-indent 2
verilog-cexp-indent 2
verilog-compiler "echo 'No verilog-compiler set, see "M-x describe-variable verilog-compiler"'"
verilog-coverage "echo 'No verilog-coverage set, see "M-x describe-variable verilog-coverage"'"
verilog-delete-auto-hook nil
verilog-getopt-flags-hook nil
verilog-highlight-grouping-keywords nil
verilog-highlight-p1800-keywords nil
verilog-highlight-translate-off nil
verilog-indent-begin-after-if t
verilog-indent-declaration-macros nil
verilog-indent-level 3
verilog-indent-level-behavioral 3
verilog-indent-level-declaration 3
verilog-indent-level-directive 1
verilog-indent-level-module 3
verilog-indent-lists t
verilog-library-directories '(".")
verilog-library-extensions '(".v" ".sv")
verilog-library-files nil
verilog-library-flags '("")
verilog-linter "echo 'No verilog-linter set, see "M-x describe-variable verilog-linter"'"
verilog-minimum-comment-distance 40
verilog-mode-hook 'verilog-set-compile-command
verilog-simulator "echo 'No verilog-simulator set, see "M-x describe-variable verilog-simulator"'"
verilog-tab-always-indent t
verilog-tab-to-comment nil
verilog-typedef-regexp nil
)

Author Name: yiftach Maayan
Original Redmine Message: 90 from https://www.veripool.org

My question is how to preserve comment via hierarchies in Emacs Verilog autoinst?
The comments I get say where the signal comes from or goes to.
I would like to have the option of extracting the comment from sub modules.
E.g.

+Top module+

/*autooutput*/
// Beginning of automatic outputs (from unused autoinst outputs)
output  solenoid2;		// control solenoid on/off operation extracted comment
// End of automatics

….

solenoid_driver
       solenoid_driver_u32(/*autoinst*/
     // Outputs
.solenoid(solenoid),
….

+Sub module+

module solenoid_driver(/*autoarg*/
    // Outputs
    solenoid, 
    // Inputs
    solenoid_en, clk, reset_n
    );   
    output reg       solenoid; // control solenoid on/off operation extracted comment

Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 95 from https://www.veripool.org
Original Date: 2009-06-04
Original Assignee: Michael McNamara

(* ... *) indents incorrectly.

See http://www.veripool.org/boards/14/topics/137

Author Name: Amir peleg
Original Redmine Message: 399 from https://www.veripool.org

Hi ,
Im trying to upcase the @ Variable as following

/*
     ctrl2 AUTO_TEMPLATE "\([a-zA-Z]+$\)"
                          (
			    .apb_prdata		(prdata[`APB_INTC_@_PORT]), // I would like that the @ will be in upper case
                             .apb_\([a-z]\)      (\1_@),	// here i need it to be same as grabbed		 
 );
*/
 

ctrl2 
     ctrl2_h (/*AUTOINST*/);

ctrl2 
     ctrl2_l (/*AUTOINST*/);

Please Advice
Thanks

Author Name: David Rogoff
Original Redmine Issue: 245 from https://www.veripool.org
Original Date: 2010-04-18
Original Assignee: Wilson Snyder (@wsnyder)

Hi Wilson.

I asked for this a year ago as along with the modport stuff you added (thanks!) in Issue #75. As I, and other engineers I work with, have done a ton more SV code, I'm going to ask again, since it would really help in spotting renaming of signals through hierarchies.

Original request:

Use, if specified (SVD variable??) .name port connections for any port connected to a signal with the same name, which would be anything in AUTOINST not using a template:

module top;
    myram myram0(
     /*AUTOINST*/
       // Interfaces
       .ram_if        (ram_if.slave),

       // Inputs
       .clk,
       .reset);

This is nice because it makes it obvious which ports connect to signals that have a different name. Of course you can just use .*, but I've threatened to shoot anyone in my group who uses that since it makes code totally unreadable.

You replied

I don't want to do this (yet) because it would break Verilog 2001 files, and there's no reliable way to tell which language is in use. Also, it would mess up AUTOWIRE.

I'd suggest again, that this could be a config variable for verilog-mode to enable.

Thanks,

David

Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 180 from https://www.veripool.org
Original Date: 2009-11-10
Original Assignee: Michael McNamara

The signed and unsigned keywords seem to confuse indentations of structs.

struct packed {
    int a;  // ok
};
struct packed signed {
                       int a;  // woops
};
struct packed unsigned {
                       int a;  // woops
};

Author Name: Joachim Lechner
Original Redmine Issue: 260 from https://www.veripool.org
Original Date: 2010-06-04
Original Assignee: Michael McNamara

It would be nice to have the autoformat/indent feature also for verilog 2001 module headers.

e.g.:

module test_module(
  input wire [1:0]      pin1,
  input wire      pin2,
  input wire [1:0]      pin3,
  input wire        pin4,
  output wire     pin5,
  output wire [10:0] pin6,
  output reg     pin7,
  output reg  [1:0]     pin8
  );

to something like:

module test_module(
  input  wire [1:0]  pin1,
  input  wire        pin2,
  input  wire [1:0]  pin3,
  input  wire        pin4,
  output wire        pin5,
  output wire [10:0] pin6,
  output reg         pin7,
  output reg  [1:0]  pin8
  );

Best regards, Joachim

Author Name: P Jay
Original Redmine Message: 393 from https://www.veripool.org

Could anyone help me to get /AUTOPERL .../ to work with emacs. AUTOINSERTLISP works fine. But I could not insert a text based on the perl script. Do I need to have any include files or what is the command line I should use to expand AUTOPERL.
My code:
/*AUTOPERL
for($i=0;$i<5;$i++)
print "assign signal_A[$i] = signal_B[$i];\n";
*/

It does not expand if I use command line
emacs --batch tb.v -f verilog-batch-auto

Please help me.