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Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

License: MIT License

Verilog 100.00%

full-adder 4-bit-parallel-adder binary-to-gray 4-bit-combinational-adder bcd-to-7-segment 4-bit-comparator adder-subtractor carry-look-ahead-adder carry-select-adder 32-bit-fast-adder

verilog-hdl-lab-experiments's Introduction

Hi , I'm Vedant Anant Sontake

About me

I'm a pre-final year student, pursuing my B.Tech. in Electrical Engineering at IIT Jodhpur
I'm proficient in multiple programming languages like C++, Python
I'm skilled in Data structures and Algorithms, Pattern Recognition and Machine Learning and Front-end web development
I'm currently learning about Back-end web development, Web3 and DApps

Let's connect

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verilog-hdl-lab-experiments's Issues

Update README.md of Barrel Shifter

README format:

Introduction: Describe the circuit in few lines
Truth table: Create a center aligned truth table for the given circuit
Schematic and Realization of Circuit: Attach an image of the schematic and realization of the given circuit. Source should be cited in case image is taken from web.

Reference:

Refer to these README files for more clarity regarding format.

Update README.md of Priority encoder

README format:

Introduction: Describe the circuit in few lines
Truth table: Create a center aligned truth table for the given circuit
Schematic and Realization of Circuit: Attach an image of the schematic and realization of the given circuit. Source should be cited in case image is taken from web.

Reference:

Refer to these README files for more clarity regarding format.

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