A2Pico is about Apple II peripheral cards based on the Raspberry Pi Pico. It consists of two parts:

• Several hardware reference designs
• A software library for projects based on A2Pico

Soon after the introduction of the Raspberry Pi Pico in 2021 Glenn Jones and I started to experiment with directly connecting it to the Apple II slot bus. In 2022 I published a working Pico firmware on GitHub. Based on that we started to implement the A2retroNET project which I presented at KanasFest 2023 (https://youtu.be/UMr2erIUDwU).

In the meanwhile Ralle Palaveev created his own A2Pico hardware for the firmware I had published before. In contrast to the hardware I presented on KansasFest, A2Pico consists completely of through-hole components which allow for very easy DIY assembly. However, at that point my Pico firmware relied on the behavior of components only available as SMD fine-pitch packages. Therefore A2Pico had some functional limitations.

Considering the next steps after presenting the prototype at KansasFest I decided that my firmware should be accessible to the DIY community so I teamed up with Ralle to modify both hardware and firmware to enable full functionlity with through-hole components.

Additionally I wanted to establish a software library that avoids duplication of low level code into the different firmware projects that all share the same hardware. The name A2Pico is now used for both the common hardware and the common software.

• Most recent TH design
• Most recent SMD design

/DEVSEL, /IOSEL and /IOSTRB are combined to ENBL via an AND gate. A0-A7 and D0-D7 are multiplexed to the same GPIOs. D0-D7 direction is controlled by GPIO.

• A2retroNET (https://github.com/oliverschmidt/a2retronet)
• Apple2-IO-RPi (https://github.com/oliverschmidt/apple2-io-rpi)
• Apple II Pi (https://github.com/oliverschmidt/apple2pi)
• softSP (https://github.com/oliverschmidt/softsp)
• A2Pico Demo (https://github.com/oliverschmidt/a2pico/tree/main/demo)

There are three PIO state machines: addr, read and write. The ARM core 0 is operated in a traditional way: Running from cached Flash, calling into the C library, being interrupted by the USB library, etc. However, The ARM core 1 is dedicated to interact with the three PIO state machines. Therefore it runs from RAM, calls only inline functions and is never interrupted.

On the falling edge of ENBL, the the addr state machine samples lines A0-A11 plus R/W and pushes the data into its RX FIFO. In case of a 6502 write cycle, it additionally triggers the write state machine. The ARM core 1 waits on that FIFO, decodes the address parts and branches based on R/W.

In case of a 6502 write cycle, the write state machine samples lines D0-D7 ~300ns later and pushes the byte into its RX FIFO. By then, the ARM core 1 waits on that FIFO and processes the byte.

In case of a 6502 read cycle, it's up to the ARM core 1 code to produce a byte in time for the 6502 to pick it up. As soon as it has done so, it pushes the byte into the read state machine TX FIFO. That state machine waits on its TX FIFO and drives out the byte to the lines D0-D7 until the rising edge of ENBL.