thinkoco / c5soc_opencl Goto Github PK

@thinkoco
Sir, is there BSP for De0-nano-soc board that is downloadble online?
Thank you.

I try to test the hello_world program from intel web site

Following Code Running on the DE10-Nano Board use the default image. (No VIP)
I chose that so I can try my opencl code interactively.
I run these code from Serial Terminal
ogin as knat / knat then sudo su
change to root folder
source the 17.1.sh

root@C5SoC:~# aocl list-devices
Verified that the kernel mode driver is installed on the host machine.

Using platform: Intel(R) FPGA SDK for OpenCL(TM)
Board vendor name: Intel(R) Corporation
Board name: de10_nano_sharedonly_hdmi : Cyclone V SoC Development Kit

Buffer read/write test passed.

DIAGNOSTIC_PASSED

I try to connect to HDMI , it realy has no output
I wonder the board name is wrong it suppose to be de10_nano_sharedonly

root@C5SoC:~# aocl env hello_world.aocx
INPUT_ARGS=device/hello_world.cl -o bin/hello_world.aocx -board c5soc_sharedonly --report

I compile the aocx use board type s5soc_sharedonly because I don't knwo which to chose.
the board type has no de10_nano_shareonly to choice.
The aocx file build after aocl program to the fpga board, It hang.
Can you give us some readme about how to use your image without VIP core.

Hi,
I downloaded the "c5soc_opencl_lxde_fpga_reconfigurable.img" file and written it to the SD card. After that, i copied the rbf and dtb files to the FAT32 partition. However, i encountered this problem.

What seems to be the problem? Thank you.

What would be required to make this work with the D8M-GPIP terrasic camera?

I have tried sobel and its all good. But, when i try colorAPP. I get the following error.

ERROR: CL_INVALID_KERNEL_NAME
Line 246

However, i checked the host code. The name is same as the files name.
@thinkoco help please :)

I installed the Quartus 16.1 lite edition(No License required). But in compiling process(make .aocx file) it asking for license file. Some one please help me to solve this problem.

Hi, thinkoco
I've followed your guide: https://github.com/thinkoco/c5soc_opencl/blob/master/documents/HowToBuildSDImage.md to build lxde image. But when I boot the image to de1 and use VGA to connect the monitor but there is no desktop environment. But when I copy your root files in your lxde image to my image, i get desktop environment. So I want to ask that did you config anything in your root files??
And one more thing that when i install rsyslog i got this error?

So I've removed rsyslogy and there is any problem with my image if i don't install rsyslog?
Thanks you!

Mr Thinkoco, some questions about HowToBuildBSP.md，希望在有空的时候可以指导下，3KS
1）在添加8bit LED_PIO之前，其实你还添加了avalon-mm pipeline bridge, So how about the Pipeline's configuration(Width, Address and so on)
2）在第9点中，下面你还多了memory和periphral，这是什么时候添加的，以及如何互联总线

3）原始的iface也是个Qsys，是Terasic做的，你在他的基础上增加了VIP IP以支持VGA/HDMI功能，这一部分有没有相关的tourial
4）我竟然没有在Terasic的 CD中找到关于iface的制作的相关手册。
5）如果不用shareonly，而是ARM与FPGA的DDR/SDRAM分开，应该可以达到更高的带宽与效率，所以为什么都用shareonly
6）c5iface.ipx是个啥？

谢谢，我主要是弄裸奔FPGA硬件加速的，七八年前摸过SOPC后来在没弄过，这一块不太熟。

Dear thinkoco,
In the step
"Copy the BOARD_NAME_APP.rbf and BOARD_NAME_socfpga.dtb in sdcard ( make sure the BOARD_NAME same as your target board) to Windows fat32 partition and rename them to opencl.rbf and socfpga.dtb".
Q1. What is ther "Windows fat32 partition"? My personal desktop or the microSD card?
Q2. If the "Windows fat32 partition" were the SD card , I should replace the original "opencl.rbf" and "socfpga.dtb" with files which has the same name?
Thanks a lot !!

Hello， Thankoco：
Ths for your achievements about multi fpga kit‘s bsp which support vga and desktop, and I‘m working on DE10-Standard with donny's PipeCNN.
After I modified PipeCNN‘s conv_pipe.cl， it can support Quartus 17.1 OpenCL modify and succesfully.

Everything seems OK while it goes error wirh "Error: Qsys-script FAILD"， after I refer the conv_pipe.log for details， I have found that it goes wrong while generate Qsys system. So I open the Project of de10_standard_sharedonly_vga, found that Qsys(Platform Designer) has serveal error, about acl iface interface, the error is like this:

As you said de10_standard_sharedonly_vga is both supprt 16.1 & 17.1 , but there is sth. wrong while open or compile with 17.1, what's wrong with me, or there is some options that I should set ?

TKS. best regards.

Hi there, I am trying to get this to work with OpenCL SDK 17.1 on my de10-nano board, but am having trouble. I am trying to run this project: https://github.com/doonny/PipeCNN.

I was able to successfully get it working using the OpenCL image for the de10 nano provided by terasic, but unfortunately that image doesnt support HDMI and ethernet. I cross-compiled the PipeCNN kernel and host using Intel OpenCL SDK 17.1 and the de10-nano BSP on my desktop and transferred to the de10-nano board. It successfully ran there, even though it had the 16.1 binaries.

I then tried using this repo's BSP and followed the instructions here, recompiling the PipeCNN kernel with the de10_nano_sharedonly_hdmi BSP from this repo. However, it would give this error:
libintel_soc32_mmd.so cannot opened shared object file: no such file or directory
and various other errors. Im guessing this error is because that file used to be called libalterammdpcie.so but intel changed a bunch of the names in 17.1. So, I tried recompiling the kernel drivers for 17.1 (zImage, socfpga.dtb, and opencl.rbf) as well as getting the latest aocl binaries from intel for 17.1. I was finally able to get PipeCNN to run, however the execution gets stuck on layer 1. You can read more about that here: doonny/PipeCNN#53.

Do you know what steps I'm missing to get this working with 17.1? Unfortunately I cant do 16.1 because of licensing issues that were not able to be resolved with the eth0 fix. Intel removed the requirement for licensing in 17.1 when using aoc, so thats the only choice I have.

I am using this image: c5soc_opencl_lxde_fpga_reconfigurable.img

But, the partition sizes are not very big, and the 2nd partition is the one with the Linux root FS on it, but there is a 3rd partition that has some required code on it (I can't remove it or the image won't boot at all), so I can't expand the root fs.

I'd like to re-build this image and re-order the partitions if possible so that the root fs is last.

Any thoughts, or information on who built this?

Hi,
I am having a project using Intel FPGA for OpenCL code for DE 10 Standard. I am new to FPGA so I would like to ask some questions
It is possible to connect Camera on usb port on PC, transfer data from PC to DE 10 board for processing, then get back the result and display on PC ?. So I don't need to use HPS on FPGA since I should connect the board to robot, get data from camera on robot and the implementation should be integrated on ROS (Robot Operating System)
Thank you

Hi，你好。我想了解下，是什么原因不支持DE0-nano开发板呢？谢谢

Hi thinkoco,
is it possible to modify driver or any way for dual USB camera application ?
Thanks a lot !!

Hi @thinkoco,
I've download BSP(Board Support Package) for Altera SDK OpenCL 18.1 and followed DE1-SoC OpenCL User Manual to build hello example (there is the link to download this manual:http://download.terasic.com/downloads/cd-rom/de1-soc/linux_BSP/OPENCL18.1/DE1-SoC_OpenCL_v05.pdf). I've successfully generated hello_world.aocx and host file. But when i execute it in your image c5soc_opencl_lxde_fpga_reconfigurable_20201027.img, i got this error this error:

Hi thinkoco,
I tested the terasic DE1 Board with the
opencv Camera in example.
I tested 3 Webcams,
1 worked fine
1 seems to have the wrong sync-rate (or something that makes the picture scrambling)
1 crashed when starting the app.
Is there a way to config the camera driver ?
best regards
hauke

@HammadJ The BSP is OK , but there is something wrong with my sd card iamge. I have fixed this issue.U can run with the latest SD card image here . Read the readme.txt in sd card first！
opencl runtime is 17.1

Originally posted by @thinkoco in #4 (comment)

@HammadJ The BSP is OK , but there is something wrong with my sd card iamge. I have fixed this issue.U can run with the latest SD card image here . Read the readme.txt in sd card first！
opencl runtime is 17.1

Originally posted by @thinkoco in #4 (comment)

Hi @thinkoco,
I want to process an OpenCL project on the DE1SOC board for a class assignment.

After two days of setting a development environment, it seems like Quartus Prime Lite doesn't support OpenCL SDK.

Like you can't install OpenCL SDK and Quartus Prime Lite in the same directory(even you don't install the Quartus Prime Standard/Por included in OpenCL SDK), but if installed in separate directories, I can't figure out how to set environment variables properly.
It seems like you made it with Quartus Prime Lite 18.0 in your tutorial.

Do you have any idea to solve this problem?

Thanks,
Luther

My goal is to take the USB video and process it using OpenCL. In order to do this, I must take the USB camera input and put the frames into memory, where the VIP core can then access it.

My first goal would be to make a simple project without a linux GUI so that I can send the USB video direct to HDMI.

USB Video -> Software moves to Memory using AXI (Not sure how to do this... ) -> Frame reader from memory, to clock video output to HDMI

I just don't know how to do the software step, and was hoping someone could offer an example, or at least tips for getting started.

Hi,
I am trying to use OpenCL SDK 17.1 (Quartus Standard ) with De1SoC
I am having a couple of problems
OS Ubuntu
Intel SDK installation
Quartus Prime Lite 17.1
Intel FPGA SDK for OpenCL 17.1
SoC Embedded Design Suite (EDS)

1. Compiling host Application
   I have installed all the necessary cross compiler using the command provided by your documents
   sudo apt update
   sudo apt install u-boot-tools gcc-arm-linux-gnueabihf g++-arm-linux-gnueabihf libncurses5-dev make lsb uml-utilities git

after issuing make host

make host
arm-linux-gnueabihf-g++ host/src/color.o host/src/video.o host/src/AOCL_Utils.o host/src/screen.o host/src/opt.o host/src/main.o -o bin/camera_sobel.run -L/intelFPGA/17.1/hld/board/terasic/de1soc/arm32/lib -L/intelFPGA/17.1/hld/host/arm32/lib -L/intelFPGA/17.1/hld/host/arm32/lib -Wl,--no-as-needed -lalteracl -lalterahalmmd -lalterammdpcie -lelf -lstdc++ -lSDL2
/usr/lib/gcc-cross/arm-linux-gnueabihf/5/../../../../arm-linux-gnueabihf/bin/ld: cannot find -lSDL2
collect2: error: ld returned 1 exit status
Makefile:115: recipe for target 'camera_sobel.run' failed
make: *** [camera_sobel.run] Error 1

I already have installed sudo apt-get install libglib2
the problem remains same

2. Running c5soc_opencl_lxde_all_in_one_180317.img on De1Soc.
   After boot with de1soc (opecl rbf and dtd )
   I executed sobel filter using RTE 17
   Windows shows the picture
   pressing + / - / = does not have any effect.

3. if I run my opencl application .aocx it says
   libalterammd library missing

Could please help me to sort out these problems, specially I am interested to
run sobel using UVC camera using intel fpga sdk 17.1 on DE1SoC

Thanks a lot

quartus prime lite我在官网找到了下载地址，但是我在opencl的下载界面找不到lite版本的，只有standard和pro版本的。
能指点一下您是如何解决的吗？万分感谢！！！

Hello,
Thank you for creating this nice repo.. it's been very helpful. I tried to build my sd image with the following command and it failed. I followed every step in your tutorial exactly, and I am building this with Ubuntu 18.04 for my DE1 soc. The script just hangs forever and never completes:

sudo ./make_sdimage.py -f -P preloader-mkpimage.bin,u-boot.img,num=3,format=raw,size=10M,type=A2 -P rootfs/*,num=2,format=ext4,size=1500M -P zImage,u-boot.scr,opencl.rbf,socfpga.dtb,num=1,format=vfat,size=500M -s 2G -n sdcard_de1soc.img

Please let me know if you have any ideas on how to fix this.. thanks!

Hi @thinkoco
Could you tell me how can create De1-SoC linux image with OpenCL driver and init_opencl_.sh file? I have spent a lot of time looking for any documents about it but i couldn't find anything!
Thanks you!

Hi @thinkoco,
I want to open some driver in your image c5soc_opencl_lxde_fpga_reconfigurable_20201027.img. There is any way to do that without remaking the Image?
Thank you!

I was wondering if it's possible to make the DE10-Standard programmable via OpenCL using Quartus 19.1 using this repo?

It doesn't connect to the network.

c5soc_opencl_lxde_fpga_reconfigurable.img also doesn't connect.

Greetings. I'm trying to compile the camera_sobel, but getting compile errors.

I've tried using the 17.1 and 18.1 build tools versions, but I get the same error for both

edhenderson@ubuntu:~/proj/machine_learning/c5soc_opencl/application/camera_sobel$ make
arm-linux-gnueabihf-g++   -Wall -std=c++11 -O2 -c host/src/video.cpp -o host/src/video.o -I/home/edhenderson/intelFPGA/17.1/hld/host/include   -Ihost/inc  -I../common/inc  -I/usr/include/SDL2  -DFPGA_DEVICE 
host/src/video.cpp: In function ‘void video_set_format()’:
host/src/video.cpp:86:20: error: invalid conversion from ‘__u32 {aka unsigned int}’ to ‘v4l2_buf_type’ [-fpermissive]
  video.format.type = stream_flag;
                    ^
host/src/video.cpp: In function ‘void buffer_request()’:
host/src/video.cpp:156:24: error: invalid conversion from ‘__u32 {aka unsigned int}’ to ‘v4l2_buf_type’ [-fpermissive]
  video.buffer.req.type = stream_flag;
                        ^
Makefile:118: recipe for target 'host/src/video.o' failed
make: *** [host/src/video.o] Error 1
edhenderson@ubuntu:~/proj/machine_learning/c5soc_opencl/application/camera_sobel$ 

Do I need to go back to 16.x?? I'd really prefer to move forward of course. My next step is to start digging into the libraries and include files and see if I can track down the source of the error. I'm kind of thinking this is a version issue, but without more experience with OpenCL, it will take me some time to track this down.

Any advice or assistance would be much appreciated